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1. 发明申请

WO2011075452A1 3D MEMORY DEVICE WITH PAGE REGISTER NOT LIKE SENSE AMPLIFIER CIRCUITS AND SENSE AMPLIFIER INTERFACE UNDERNEATH MEMORY ARRAY 审中-公开
标题翻译：具有页面寄存器的3D存储器件不像感测放大器电路和感测放大器接口下的存储器阵列
公开(公告)号：WO2011075452A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060153
申请日：2010-12-13
申请人： SANDISK 3D LLC , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , ZHANG, Yuheng , LIU, Tz-yi , FASOLI, Luca
发明人： BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , ZHANG, Yuheng , LIU, Tz-yi , FASOLI, Luca
IPC分类号： G11C5/02 , G11C17/16 , G11C13/02 , G11C13/00
CPC分类号： G11C5/025 , B82Y10/00 , G11C5/02 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage device includes a substrate, a monolithic three- dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three- dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.
摘要翻译：非易失性存储装置包括衬底，布置在衬底的一部分上方的非易失性存储元件的单片三维存储器阵列，与非易失性存储元件通信的多个读出放大器，多个临时与读出放大器通信的存储装置，与临时存储装置通信的页寄存器，以及一个或多个控制电路。一个或多个控制电路与页寄存器，临时存储设备和读出放大器通信。读出放大器布置在单片三维存储器阵列下方的衬底上。临时存储装置布置在单片三维存储器阵列下面的衬底上。页面寄存器布置在基板上的不在单片三维存储器阵列下方的区域中。由感测放大器从非易失性存储元件读取的数据响应于一个或多个控制电路传送到临时存储设备，然后传送到页寄存器。要编程到非易失性存储元件中的数据响应于一个或多个控制电路从页寄存器传送到临时存储设备。

2. 发明申请

WO2011075453A1 PROGRAM CYCLE SKIP 审中-公开
标题翻译：程序循环跳
公开(公告)号：WO2011075453A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060155
申请日：2010-12-13
申请人： SANDISK 3D LLC , BALAKRISHNAN, Gopinath , FASOLI, Luca , LIU, Tz-yi , ZHANG, Yuheng , LI, Yan
发明人： BALAKRISHNAN, Gopinath , FASOLI, Luca , LIU, Tz-yi , ZHANG, Yuheng , LI, Yan
IPC分类号： G11C16/10 , G11C16/32 , G11C13/00 , G11C5/02 , G11C17/16
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non¬ volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应该跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

3. 发明申请

WO2010047911A1 PAGE BUFFER PROGRAM COMMAND AND METHODS TO REPROGRAM PAGES WITHOUT RE-INPUTTING DATA TO A MEMORY DEVICE 审中-公开
标题翻译：页面缓存程序命令和方法来重现数据到存储器件
公开(公告)号：WO2010047911A1
公开(公告)日：2010-04-29
申请号：PCT/US2009/057992
申请日：2009-09-23
申请人： SANDISK 3D LLC , FASOLI, Luca , ZHANG, Yuheng , BALAKRISHNAN, Gopinath
发明人： FASOLI, Luca , ZHANG, Yuheng , BALAKRISHNAN, Gopinath
IPC分类号： G11C16/10
CPC分类号： G11C16/102 , G06F12/0246
摘要： A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.
摘要翻译：一种用于在与外部主机设备通信的存储设备中有效地处理写入操作故障的技术允许从页面缓冲器将数据页面重写到存储器阵列。主机向存储设备提供用户数据，第一写地址和写命令。如果写入尝试失败，则主机提供具有新地址的重写命令，而不会将用户数据重新发送到存储设备。在来自页面缓冲器的重新写入正在进行时，可以在存储器件的数据高速缓存处接收附加数据。重新写入的数据可以在数据被读出到主机的复制操作中获得，被修改并写回存储器件。在复制操作期间可以向存储器件输入附加数据。页面缓冲区数据也可以进行修改。

4. 发明申请

WO2010042354A1 CONTINUOUS PROGRAMMING OF RESISTIVE MEMORY USING STAGGERED PRECHARGE 审中-公开
标题翻译：使用STAGGERED PRECHARGE连续编程电阻记忆
公开(公告)号：WO2010042354A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/058890
申请日：2009-09-29
申请人： SANDISK 3D LLC , FASOLI, Luca , YAN, Tianhong
发明人： FASOLI, Luca , YAN, Tianhong
IPC分类号： G11C7/12 , G11C13/00
CPC分类号： G11C7/1078 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non- volatile storage element's program operation to complete.
摘要翻译：非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。对控制线进行充电导致相应的非易失性存储元件经历程序操作。在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

5. 发明申请

WO2010123978A1 REDUCED COMPLEXITY ARRAY LINE DRIVERS FOR 3D MATRIX ARRAYS 审中-公开
标题翻译：减少复杂的阵列线驱动器为3D矩阵阵列
公开(公告)号：WO2010123978A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/031876
申请日：2010-04-21
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca
IPC分类号： G11C5/02 , G11C5/06 , G11C8/10 , G11C8/12 , G11C11/16 , G11C11/22 , G11C7/10 , G11C13/02 , G11C16/02
CPC分类号： G11C11/22 , G11C5/025 , G11C5/063 , G11C8/10 , G11C8/12 , G11C11/16 , G11C13/0002 , G11C13/0026 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.
摘要翻译：一种偏置非易失性存储器阵列的方法。非易失性存储器阵列包括第一和第二多个Y线，多个X线，第一和第二多个两个终端存储器单元。每个第一和第二存储器单元分别耦合到第一或第二多个Y线中的一个以及多个X线中的一个。基本上所有第一和第二多条Y线被驱动到Y线取消选择电压。第一多个Y线中的至少一个选择的Y线被驱动到Y线选择电压，同时浮置第一多个Y线的剩余Y线，同时驱动基本上所有第二多条Y线到Y线取消选择电压。

6. 发明申请

WO2011156343A2 NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF 审中-公开
标题翻译：具有读取/写入元件的3D阵列的非易失性存储器及其读取/写入电路及其方法
公开(公告)号：WO2011156343A2
公开(公告)日：2011-12-15
申请号：PCT/US2011/039405
申请日：2011-06-07
申请人： SANDISK 3D LLC , SAMACHISA, George , FASOLI, Luca , LI, Yan , YAN, Tianhong
发明人： SAMACHISA, George , FASOLI, Luca , LI, Yan , YAN, Tianhong
IPC分类号： G11C11/16 , G11C13/02
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0097 , G11C16/06 , G11C2013/0054 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
摘要翻译：三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

7. 发明申请

WO2011156357A1 NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH EFFICIENT DECODING OF VERTICAL BIT LINES AND WORD LINES 审中-公开
标题翻译：具有读取/写入元素的3D阵列的非易失性存储器，用于高效地解码垂直位线和字线
公开(公告)号：WO2011156357A1
公开(公告)日：2011-12-15
申请号：PCT/US2011/039423
申请日：2011-06-07
申请人： SANDISK 3D LLC , SAMACHISA, George , FASOLI, Luca , HIGASHITANI, Masaaki , SCHEUERLEIN, Roy Edwin
发明人： SAMACHISA, George , FASOLI, Luca , HIGASHITANI, Masaaki , SCHEUERLEIN, Roy Edwin
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C16/10 , G11C13/003 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/149
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines (331, 332) from the substrate through the multiple layers of planes. A first set of pillar lines (331) acts as local bit lines for accessing the memory elements together with an array of word lines (340) on each plane. A second set of pillar lines (332) is connected to the word lines (340). An array of metal lines (251, 252) on the substrate is switchable connected to the pillar lines to provide access to the first (331) and second (332) sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储元件响应于在其上施加的电压差而可逆地改变电导级。三维阵列包括从衬底通过多层平面的柱线（331,332）的二维阵列。第一组柱线（331）用作用于在每个平面上与字线（340）阵列一起存取存储元件的局部位线。第二组柱线（332）连接到字线（340）。衬底上的金属线阵列（251,252）可切换地连接到柱线以提供对第一（331）和第二（332）组立柱线路的通路，从而分别提供对位线和字的访问线的三维阵列。

8. 发明申请

WO2010123517A1 MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEME 审中-公开
标题翻译：具有数据线切换方案的存储器系统
公开(公告)号：WO2010123517A1
公开(公告)日：2010-10-28
申请号：PCT/US2009/058889
申请日：2009-09-29
申请人： SANDISK 3D LLC , YAN, Tianhong , FASOLI, Luca
发明人： YAN, Tianhong , FASOLI, Luca
IPC分类号： G11C8/12 , G11C13/00
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了增加存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。独立检测每组的第一非易失性存储元件的存储器操作的完成。在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

9. 发明申请

WO2012051041A1 MULTI-LEVEL MEMORY ARRAYS WITH MEMORY CELLS THAT EMPLOY BIPOLAR STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有使用双极存储元件的存储器单元的多级存储器阵列及其形成方法
公开(公告)号：WO2012051041A1
公开(公告)日：2012-04-19
申请号：PCT/US2011/055076
申请日：2011-10-06
申请人： SANDISK 3D, LLC , CHEN, Yung-Tin , MIHNEA, Andrei , SCHEUERLEIN, Roy E. , FASOLI, Luca
发明人： CHEN, Yung-Tin , MIHNEA, Andrei , SCHEUERLEIN, Roy E. , FASOLI, Luca
IPC分类号： H01L27/24 , H01L45/00 , G11C13/00
CPC分类号： H01L27/2481 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A memory array is provided that includes a first memory cell (200-1) having a first conductive line (202a); a first bipolar storage element (102-1) formed above the first conductive line; and a second conductive line (302) formed above the first bipolar storage element; and a second memory cell (200-2) formed above the first memory cell and having a second bipolar storage element (102-2) formed above the second conductive line; and a third conductive line (202b) formed above the second bipolar storage element. The first and second memory cells share the second conductive line (302); the first bipolar storage element (102-1) has a first storage element polarity orientation within the first memory cell; the second bipolar storage element (102-2) has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation.
摘要翻译：提供一种存储器阵列，其包括具有第一导线（202a）的第一存储单元（200-1）; 形成在第一导线上方的第一双极存储元件（102-1）; 和形成在所述第一双极存储元件上方的第二导线（302）; 以及形成在所述第一存储单元上方并具有形成在所述第二导线上方的第二双极存储元件（102-2）的第二存储单元（200-2）以及形成在所述第二双极存储元件上方的第三导线（202b）。第一和第二存储单元共享第二导线（302）; 第一双极存储元件（102-1）在第一存储单元内具有第一存储元件极性取向; 第二双极存储元件（102-2）在第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。

10. 发明申请

WO2011019623A1 SEMICONDUCTOR MEMORY WITH IMPROVED MEMORY BLOCK SWITCHING 审中-公开
标题翻译：具有改进的存储器块切换的半导体存储器
公开(公告)号：WO2011019623A1
公开(公告)日：2011-02-17
申请号：PCT/US2010/044815
申请日：2010-08-06
申请人： SANDISK 3D LLC , YAN, Thomas , FASOLI, Luca , SCHEUERLEIN, Roy, E.
发明人： YAN, Thomas , FASOLI, Luca , SCHEUERLEIN, Roy, E.
IPC分类号： G11C5/14 , G11C7/12 , G11C13/00 , G11C16/02 , G11C16/24 , G11C17/06 , G11C17/18
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译：非易失性存储器核心包括一个或多个存储器空间。每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。在存储器操作期间，存储器块被转换为活动状态和非活动状态。将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一存储块之间的电荷共享成为可能。这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

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