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1. 发明申请

WO2004111856A1 MEMORY DEVICE SUPPORTING A DYNAMICALLY CONFIGURABLE CORE ORGANISATION 审中-公开
标题翻译：支持动态可配置核心组织的内存设备
公开(公告)号：WO2004111856A1
公开(公告)日：2004-12-23
申请号：PCT/US2003/020599
申请日：2003-06-26
申请人： RAMBUS, INC. , PEREGO, Richard, E. , STARK, Donald, C. , WARE, Frederick, A.
发明人： PEREGO, Richard, E. , STARK, Donald, C. , WARE, Frederick, A.
IPC分类号： G06F12/04
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system (300) in which the memory core (305) organization changes with device width. The number of physical banks (PBO-PB3) accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logical memory banks (LBO-LB3) for narrow memory widths reduces the likelihood if bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统（300），其中存储器核心（305）组织随设备宽度而变化。访问的物理存储区（PBO-PB3）的数量随设备宽度而减少，从而减少了相对较窄内存配置的功耗。为了缩小存储器宽度，增加逻辑存储体（LBO-LB3）的数量减少了银行冲突的可能性，从而提高了速度性能。

2. 发明申请

WO2005072329A3 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 审中-公开
公开(公告)号：WO2005072329A3
公开(公告)日：2005-08-11
申请号：PCT/US2005/002301
申请日：2005-01-25
申请人： RAMBUS, INC. , WARE, Frederick, A. , PEREGO, Richard, E. , HAMPEL, Craig, E.
发明人： WARE, Frederick, A. , PEREGO, Richard, E. , HAMPEL, Craig, E.
IPC分类号： H04B3/00
摘要： A method provides for execution of calibration cycles during normal operation of the communication channel (1002). A calibration cycle includes de-coupling the normal data source (1010) from the transmitter (1003) and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver (1004) on the second component (1001). A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel (1002). For bidirectional links, calibration cycles are executed which include the step of storing received calibration pattern on the second component (1001), and retransmitting such calibration back to the first component (1000) for use in adjusting parameter of the channel at first component (1000).

3. 发明申请

WO2005072299A2 PERIODIC CALIBRATION FOR COMMUNICATION CHANNELS BY DRIFT TRACKING 审中-公开
标题翻译：通过跟踪进行通信通道的定期校准
公开(公告)号：WO2005072299A2
公开(公告)日：2005-08-11
申请号：PCT/US2005/002139
申请日：2005-01-25
申请人： RAMBUS, INC. , HAMPEL, Craig, E. , WARE, Frederick, A. , PEREGO, Richard, E.
发明人： HAMPEL, Craig, E. , WARE, Frederick, A. , PEREGO, Richard, E.
IPC分类号： H04B1/38 , H04L7/00 , H04L7/04 , H04L7/10 , H04L27/00
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2 N -1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译：一种提供执行第一校准序列的方法和系统，例如在系统初始化时建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量在参数中漂移，并根据测量的漂移更新操作值。与第一校准序列相比，第二校准序列使用较少的通信信道资源。在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2 N比特的伪随机比特序列，其中N等于大于等于7，而第二校准序列使用短校准模式，例如小于16字节的固定码，例如短至2字节长。

4. 发明申请

WO2008127698A2 MEMORY SYSTEM WITH POINT-TO-POINT REQUEST INTERCONNECT 审中-公开
标题翻译：具有点到点请求互连的存储系统
公开(公告)号：WO2008127698A2
公开(公告)日：2008-10-23
申请号：PCT/US2008/004790
申请日：2008-04-11
申请人： RAMBUS INC. , PEREGO, Richard, E. , WARE, Frederick, A.
发明人： PEREGO, Richard, E. , WARE, Frederick, A.
IPC分类号： G11C5/06 , G11C7/10 , G06F13/16
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

5. 发明申请

WO2004034401A2 DYNAMIC MEMORY SUPPORTING SIMULTANEOUS REFRESH AND DATA-ACCESS TRANSACTIONS 审中-公开
标题翻译：动态内存支持同时刷新和数据访问交易
公开(公告)号：WO2004034401A2
公开(公告)日：2004-04-22
申请号：PCT/US2003/032205
申请日：2003-10-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PEREGO, Richard, E.
发明人： WARE, Frederick, A. , PEREGO, Richard, E.
IPC分类号： G11C
CPC分类号： G11C11/406 , G06F12/00 , G06F13/1605 , G11C11/40603
摘要： Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.
摘要翻译：描述了执行重叠刷新和数据访问（读或写）事务的动态存储器系统，其最小化刷新事务对存储器性能的影响。存储器系统支持针对不同银行的独立且同时的激活和预充电操作。两组地址寄存器使系统能够同时指定用于刷新和数据访问事务的不同库。

6. 发明申请

WO2013028827A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
标题翻译：将外部功能映射到记忆体界面的方法和系统
公开(公告)号：WO2013028827A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052000
申请日：2012-08-23
申请人： RAMBUS INC. , PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
发明人： PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
IPC分类号： G06F13/14 , G06F13/16 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
摘要翻译：存储器系统包括将命令和地址传送到主存储器模块的CPU。该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。

7. 发明申请

WO2012151001A1 CONFIGURABLE, ERROR-TOLERANT MEMORY CONTROL 审中-公开
标题翻译：可配置，容错的内存控制
公开(公告)号：WO2012151001A1
公开(公告)日：2012-11-08
申请号：PCT/US2012/028658
申请日：2012-03-10
申请人： RAMBUS INC. , PEREGO, Richard, E.
发明人： PEREGO, Richard, E.
IPC分类号： G06F13/14 , G06F13/16 , G06F11/08 , G06F12/00
CPC分类号： H03M13/356 , G06F11/10 , G06F11/1666
摘要： Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.
摘要翻译：存储器系统的组件之间的可配置的，容错的通信存储器控制信息。控制器组件和存储器组件各自具有与错误检测/校正（EDC）通道一起操作的可变宽度命令/地址（CA）接口，以实现关于命令/地址信息的可变级别的错误检测和校正由于CA接口的宽度被调整，在两个部件之间传送。

8. 发明申请

WO2013028854A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
标题翻译：用于将外围功能映射到遗传存储器接口的方法和系统
公开(公告)号：WO2013028854A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052052
申请日：2012-08-23
申请人： Rambus Inc. , PEREGO, Richard, E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
发明人： PEREGO, Richard, E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G06F13/14 , G06F13/38 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
摘要翻译：存储器系统包括将命令和地址传送到主存储器模块的CPU。该模块包含一个缓冲电路，用于在CPU和主存储器之间中继命令和数据。存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持诸如图形处理等外围功能，以提高整体系统性能。缓冲电路有助于CPU和外设处理器之间的指令和数据通信，其方式可以最大限度地减少或消除修改CPU的需求，从而降低采用具有集成处理能力的主内存模块的实际障碍。

9. 发明申请

WO2009067386A1 BIDIRECTIONAL MEMORY INTERFACE WITH GLITCH TOLERANT BIT SLICE CIRCUITS 审中-公开
标题翻译：双向存储器接口，带有宽容比特片电路
公开(公告)号：WO2009067386A1
公开(公告)日：2009-05-28
申请号：PCT/US2008/083626
申请日：2008-11-14
申请人： RAMBUS INC. , CHANG, Kun-Yung , SHEN, Jie , LEE, Hae-Chang , ASSADERAGHI, Fariborz , PEREGO, Richard, E. , CHUN, Jung-Hoon
发明人： CHANG, Kun-Yung , SHEN, Jie , LEE, Hae-Chang , ASSADERAGHI, Fariborz , PEREGO, Richard, E. , CHUN, Jung-Hoon
IPC分类号： G06F13/16
CPC分类号： G06F13/1689
摘要： A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation.
摘要翻译：描述了具有发送和接收操作模式的位分片电路。所述位片电路包括：第一发射电路和在第一时钟域中操作的第一接收电路，其中所述第一电路接收第一时钟信号; 第二发送电路和在第二时钟域中操作的第二接收电路，其中所述第二电路接收第二时钟信号; 发射转换电路和接收转换电路，所述发射转换电路将所述第一发射电路耦合到所述第二发射电路，所述接收转换电路将所述第一接收电路耦合到所述第二接收电路，其中所述转换电路接收所述第一和第二时钟信号; 以及产生所述第二时钟信号的单相混频器，其中所述第二时钟信号具有所述发送操作模式中的第一相位和所述接收操作模式中的第二相位。

10. 发明申请

WO2008153652A2 REFERENCE CLOCK AND COMMAND WORD ALIGNMENT 审中-公开
标题翻译：参考时钟和命令字对齐
公开(公告)号：WO2008153652A2
公开(公告)日：2008-12-18
申请号：PCT/US2008/005985
申请日：2008-05-08
申请人： RAMBUS INC. , KIZER, Jade, M. , PEREGO, Richard, E.
发明人： KIZER, Jade, M. , PEREGO, Richard, E.
IPC分类号： G11C7/10 , G11C7/22 , H04L7/033
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0891 , H03L7/18
摘要： A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.
摘要翻译：存储器系统包括向存储器件发出命令信号和参考时钟信号的存储器控制器。参考时钟信号的边沿速率低于命令信号的比特率，因此存储器件将参考时钟信号相乘以产生用于对输入的命令信号进行采样的命令恢复时钟信号。存储器控制器将命令信号发出为与参考时钟信号的边缘对准的一系列多位命令字，使得存储器件可以使用参考时钟信号的边沿进行命令字对准。

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