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1. 发明申请

WO2017213798A1 FAST CLOCK AND DATA RECOVERY FOR FREE-SPACE OPTICAL COMMUNICATIONS 审中-公开
标题翻译：用于自由空间光通信的快速时钟和数据恢复
公开(公告)号：WO2017213798A1
公开(公告)日：2017-12-14
申请号：PCT/US2017/032500
申请日：2017-05-12
申请人： GOOGLE LLC
发明人： YANG, Sheng-hui , ZHOU, Leon
IPC分类号： H04L7/00 , H04B10/11 , H03L7/14 , H04L7/04
CPC分类号： H04L7/0075 , H04B10/11 , H04B10/112 , H04L7/0016 , H04L7/0029 , H04L7/0083 , H04L7/033 , H04L7/0331 , H04L7/10
摘要： A method includes receiving an optical signal (20) through an optical link (22) and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving power threshold and transitioning a clock and data recovery circuit (400) from a normal mode to a holdover mode when the receiving power is less than the first receiving power threshold. The clock and data recovery circuit, when operating in the holdover mode, is configured to hold a recovered clock (322) to a known-good clock frequency. When the receiving power for the optical link is greater than a second receiving power threshold, initiating a transition of the clock and data recovery circuit from the holdover mode to the normal mode and reacquiring synchronization between the recovered clock and a current rate of the incoming data stream using the known-good clock frequency.
摘要翻译：一种方法包括通过光链路（22）接收光信号（20）并确定光链路的接收功率。该方法还包括：比较光链路的接收功率与第一接收功率阈值，并且当接收功率小于第一接收功率阈值时，将时钟和数据恢复电路（400）从正常模式转换到保持模式。时钟和数据恢复电路在保持模式下操作时被配置为将恢复的时钟（322）保持到已知的时钟频率。当用于光链路的接收功率大于第二接收功率阈值时，启动时钟和数据恢复电路从保持模式到正常模式的转换并重新获得恢复的时钟与输入数据的当前速率之间的同步使用已知良好的时钟频率流。

2. 发明申请

WO2017172171A1 SELF-ADAPTING BAUD RATE 审中-公开
标题翻译：自适应波特率
公开(公告)号：WO2017172171A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/019774
申请日：2017-02-27
申请人： INTEL IP CORPORATION
发明人： LIU, Chunhui , LI, Chengzhou , JECHOUX, Bruno
IPC分类号： H04L1/00 , H04L1/20 , H04L7/00
CPC分类号： H04L12/4013 , H04J11/00 , H04J11/0023 , H04L7/0016 , H04W84/12
摘要： In an example, there is disclosed an apparatus, having: a first network interface, having a first clock and a local communication driver to communicatively couple the first network interface to a second network interface having a second clock; and one or more logic elements, including at least one hardware logic element, providing a synchronization engine to: send a first plurality of data words from the first wireless interface to the second wireless interface via the local communication driver; receive back from the second wireless interface a second plurality of data words; assign a plurality of error rates to the data words of the second plurality of data words, the plurality of error rates indicating match or mismatch; identify a range of least error values within the plurality of error rates; and select an agreed baud rate from within the range.
摘要翻译：在一个示例中，公开了一种装置，具有：第一网络接口，具有第一时钟和本地通信驱动器，以将第一网络接口通信地耦合到具有第二时钟的第二网络接口 ; 以及一个或多个逻辑元件，包括至少一个硬件逻辑元件，提供同步引擎以：经由本地通信驱动器将第一多个数据字从第一无线接口发送到第二无线接口; 从第二无线接口接收第二多个数据字; 将多个错误率分配给所述第二多个数据字的数据字，所述多个错误率指示匹配或不匹配; 识别所述多个错误率内的最小错误值的范围; 并从该范围内选择一个商定的波特率。

3. 发明申请

WO2017044565A1 CALIBRATING A SERIAL INTERCONNECTION 审中-公开
标题翻译：校准串行互连
公开(公告)号：WO2017044565A1
公开(公告)日：2017-03-16
申请号：PCT/US2016/050680
申请日：2016-09-08
申请人： BLUE DANUBE SYSTEMS, INC.
发明人： BANU, Mihai
IPC分类号： H04B1/18 , H04B1/04
CPC分类号： H04L7/0016 , H01Q1/241 , H01Q21/24 , H04B1/0458 , H04B1/18 , H04B17/00 , H04B17/364 , H04L5/0048 , H04L7/033
摘要： A method for calibrating a serial interconnection system having a first node, a second node, calibration nodes that are electrically connected in series by the serial interconnection system, and connection nodes corresponding to the serially connected calibration nodes, the connection nodes electrically connected in series by the serial interconnection system, the calibration method involving: for each of the calibration nodes performing a measurement procedure involving: injecting a corresponding reference signal into that calibration node; and while the corresponding reference signal is being injected into that calibration node, measuring the phase difference of signals appearing at the first and second nodes; from the measured phase differences for the calibration nodes, computing phase corrections for each of the calibration nodes; and applying the phase corrections computed for each of the calibration nodes to the corresponding connection nodes.
摘要翻译：一种用于校准具有第一节点，第二节点，由串行互连系统串联电连接的校准节点以及对应于串行连接的校准节点的连接节点的串行互连系统的方法，所述连接节点由串行互连系统，校准方法涉及：对于每个校准节点执行测量程序，包括：将相应的参考信号注入该校准节点; 并且当对应的参考信号被注入该校准节点时，测量出现在第一和第二节点处的信号的相位差; 从校准节点的测量相位差，计算每个校准节点的相位校正; 以及将针对每个校准节点计算的相位校正应用于相应的连接节点。

4. 发明申请

WO2016138147A1 SYNCHRONIZATION THROUGH WAVEFORM CORRELATION 审中-公开
标题翻译：通过波形相关同步
公开(公告)号：WO2016138147A1
公开(公告)日：2016-09-01
申请号：PCT/US2016/019381
申请日：2016-02-24
申请人： L-3 COMMUNICATIONS CORP.
发明人： LANDON, David , NELSON, David S. , DICKSON, Robert L. , YOHO, Brian G. , CHRISTENSEN, Carl
IPC分类号： H04L7/04 , H04L25/497
CPC分类号： H04L7/0331 , H04L7/0016 , H04L7/0029 , H04L7/042 , H04L7/10
摘要： Detecting timing of a synchronization sequence included in a data stream transmitted in a noisy channel. The synchronization sequence is a known data sequence purposely injected into the data stream for synchronization. A data stream waveform, is obtained from a noisy communication channel. The data stream waveform includes an instance of a synchronization sequence waveform. One or more samples of the synchronization sequence waveform are obtained. One or more samples of a model synchronization sequence waveform are obtained. The model synchronization sequence waveform models an expected waveform for the synchronization sequence being transmitted on the communication channel by applying the synchronization sequence to a model of the communication channel. The instance of the synchronization sequence waveform is correlated with the model synchronization sequence waveform by correlating one or more samples of the synchronization sequence waveform with the one or more samples of the model synchronization sequence waveform.
摘要翻译：检测在噪声信道中发送的数据流中包括的同步序列的定时。同步序列是有意地注入到数据流中以用于同步的已知数据序列。从噪声通信信道获得数据流波形。数据流波形包括同步序列波形的实例。获得同步序列波形的一个或多个样本。获得一个或多个模型同步序列波形的样本。模型同步序列波形通过将同步序列应用于通信信道的模型来模拟在通信信道上发送的同步序列的预期波形。通过将同步序列波形的一个或多个样本与模型同步序列波形的一个或多个样本相关联，同步序列波形的实例与模型同步序列波形相关。

5. 发明申请

WO2016011036A1 MULTI-RATE CLOCK BUFFER 审中-公开
标题翻译：多速时钟缓冲器
公开(公告)号：WO2016011036A1
公开(公告)日：2016-01-21
申请号：PCT/US2015/040386
申请日：2015-07-14
申请人： FINISAR CORPORATION
发明人： KALOGERAKIS, Georgios , NGUYEN, The'Linh , MORAN, Timothy, G.
IPC分类号： H03K5/02
CPC分类号： H03K5/00006 , G06F1/10 , H03K5/02 , H04L7/0016 , H04L7/0087 , H04L7/04
摘要： A system (100) may include a driver circuit (102) configured to receive a clock signal (106). The system may also include a first tuned circuit (104a) and a second tuned circuit (104b). The first tuned circuit (104a) and the driver circuit (102) may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active (110out high) when a rate of the clock signal is within the first frequency range and to be inactive (110out low) when the rate is outside the first frequency range. Further, the second tuned circuit (104b) and the driver circuit (102) may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit (104b) may be configured to be active (110out low) when the rate is within the second frequency range and to be inactive when the rate is outside the second frequency range (110out high).
摘要翻译：系统（100）可以包括被配置为接收时钟信号（106）的驱动器电路（102）。该系统还可以包括第一调谐电路（104a）和第二调谐电路（104b）。第一调谐电路（104a）和驱动电路（102）可以根据第一频率范围进行集中调谐。当速率在第一频率范围之外时，当时钟信号的速率在第一频率范围内时，第一调谐电路可以被配置为有效（110输出高）并且不活动（110out低）。此外，第二调谐电路（104b）和驱动电路（102）可以根据与第一频率范围不同的第二频率范围进行集中调谐。第二调谐电路（104b）可以被配置为当速率在第二频率范围内时是有效的（110out低），并且当速率在第二频率范围（110out高）之外时不活动）。

6. 发明申请

WO2015065492A1 SHORTENED TRAINING FIELD PREAMBLE STRUCTURE FOR HIGH EFFICIENCY WI-FI ENVIRONMENT 审中-公开
标题翻译：用于高效无线环境的紧凑的培训领域前置结构
公开(公告)号：WO2015065492A1
公开(公告)日：2015-05-07
申请号：PCT/US2013/068312
申请日：2013-11-04
申请人： INTEL CORPORATION , AZIZI, Shahrnaz , KENNEY, Thomas J. , PERAHIA, Eldad
发明人： AZIZI, Shahrnaz , KENNEY, Thomas J. , PERAHIA, Eldad
IPC分类号： H04W56/00
CPC分类号： H04L7/0016 , H04L7/04 , H04L7/041 , H04L27/2613 , H04L27/2657 , H04W56/0035
摘要： The disclosure generally relates to a shortened training field preamble structure for high-efficiency Wi-Fi environments. In one embodiment, the disclosure relates to a communication system having a transmitter transmitting a Master-Sync packet received by stationary and mobile receivers. The Master-Sync packet contains information for communicating in a HEW environment. Upon receipt each receiver decodes the Master-Sync packet to (i) estimate a frequency offset and/or an automatic gain control (AGC) setting; (ii) select a transmission frequency consistent with the frequency offset; and/or (iii) determine a new transmission power consistent with the AGC; (iv) tune to a new frequency offset and gain control setting to receive subsequent packets from the transmitter.
摘要翻译：本公开一般涉及用于高效Wi-Fi环境的缩短的训练场前同步码结构。在一个实施例中，本公开涉及一种具有发射机的通信系统，所述发射机发送由固定和移动接收机接收的主同步分组。主同步数据包包含用于在HEW环境中通信的信息。在接收到每个接收器时，解码主同步分组以（i）估计频偏和/或自动增益控制（AGC）设置; （ii）选择与频率偏移一致的传输频率; 和/或（iii）确定与AGC一致的新传输功率; （iv）调谐到新的频率偏移和增益控制设置以接收来自发射机的后续分组。

7. 发明申请

WO2013189009A1 ADAPTIVE OFFSET SYNCHRONIZATION OF DATA BASED ON RING BUFFERS 审中-公开
标题翻译：基于环形缓冲器的数据自适应偏移同步
公开(公告)号：WO2013189009A1
公开(公告)日：2013-12-27
申请号：PCT/CN2012/077071
申请日：2012-06-18
申请人： QUALCOMM INCORPORATED , ZHOU, Mindong , FU, Guangning , WU, Wenjia
发明人： ZHOU, Mindong , FU, Guangning , WU, Wenjia
IPC分类号： G06F13/28
CPC分类号： H04L7/0016 , G06F13/385 , H04L25/4927
摘要： A method and apparatus for synchronizing operations between a first circuit and a second circuit is disclosed. The method involves writing receive data from the first circuit to a first ring buffer at a first rate. The first ring buffer has a fixed-length of buffer elements and respective read and write buffer pointers. The buffered receive data is read from the first ring buffer to the second circuit at a second data rate. The respective positions of the read and write buffer pointers are detected, and a relative position between the read and write pointers is dynamically adjusted to enforce at least a predetermined minimum spacing. The dynamic adjustment comprises selectively adding or deleting portions of the data to or from the ring buffer.
摘要翻译：公开了一种用于在第一电路和第二电路之间同步操作的方法和装置。该方法包括以第一速率将接收数据从第一电路写入第一环形缓冲器。第一个环形缓冲区具有固定长度的缓冲区元素和相应的读取和写入缓冲区指针。缓冲的接收数据以第二数据速率从第一环形缓冲器读取到第二电路。读取和写入缓冲器指针的相应位置被检测，并且动态地调整读取和写入指针之间的相对位置以执行至少预定的最小间隔。动态调整包括选择性地向环形缓冲器添加或删除数据的一部分。

8. 发明申请

WO2013169183A1 METHODS AND APPARATUS FOR DETECTING FRAME NUMBER DISCONTINUITIES BETWEEN RADIO NODES 审中-公开
标题翻译：检测无线电节点间帧数不连续的方法和设备
公开(公告)号：WO2013169183A1
公开(公告)日：2013-11-14
申请号：PCT/SE2013/050480
申请日：2013-04-30
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： CAVERNI, Alessandro , JONSSON, Anders , SHI, Nianshan , PRADAS, Jose Luis
IPC分类号： H04L1/18
CPC分类号： G06F11/0793 , G06F11/076 , H04L1/0041 , H04L1/1812 , H04L1/1874 , H04L1/1887 , H04L7/0016
摘要： A transmitting node communicates with a receiving node using a multi-layer communications protocol having a lower media access control, MAC, layer and a higher radio link control, RLC, layer. An RLC controller operates in an RLC unacknowledged mode, RLC UM. A MAC controller operates using hybrid automatic repeat request, HARQ, for transmitted MAC protocol data units. The RLC controller in the RLC UM transmits RLC protocol data units via the MAC layer. The MAC controller monitors transmission errors at the MAC layer and informs the RLC controller when detecting a predetermined number of consecutive transmission errors or a predetermined number of transmission errors during a predetermined time period so that the RLC controller can perform one or more actions.
摘要翻译：发送节点使用具有较低媒体访问控制，MAC，层和较高无线电链路控制RLC层的多层通信协议与接收节点进行通信。 RLC控制器以RLC未确认模式RLC UM操作。 MAC控制器使用针对所发送的MAC协议数据单元的混合自动重传请求HARQ进行操作。 RLC UM中的RLC控制器经由MAC层传送RLC协议数据单元。 MAC控制器监视MAC层的传输错误，并且在预定时间段期间检测到预定数量的连续传输错误或预定数量的传输错误时通知RLC控制器，使得RLC控制器可以执行一个或多个动作。

9. 发明申请

WO2013100019A1 時刻同期システム、管理ノード、及び時刻同期方法审中-公开
标题翻译：时间同步系统，管理节点和时间同步方法
公开(公告)号：WO2013100019A1
公开(公告)日：2013-07-04
申请号：PCT/JP2012/083806
申请日：2012-12-27
申请人：株式会社日立製作所
发明人：緒方　祐次 , 山田　雅毅
IPC分类号： H04L7/00 , G04G5/00 , H04L12/701
CPC分类号： H04J3/0676 , H04J3/0641 , H04J3/0658 , H04J3/0667 , H04L7/0016 , H04L67/125 , H04L69/28 , H04L69/40
摘要：複数のネットワークを用いた時刻同期システムにおいて、ネットワークの切替直後であっても適切な時刻補正を実行する時刻同期システムを提供することを目的とする。時刻マスタと時刻スレーブと管理ノードとが複数のネットワークを介して接続された時刻同期システムであって、管理ノードは、時刻パケットを送信するネットワークを切り替えると判定した場合、当該切り替え先のネットワークを特定可能な情報を時刻スレーブに通知することを特徴とする。
摘要翻译：本发明的目的是在使用多个网络的时间同步系统中，即使在网络切换之后立即执行合适的时间校正来提供时间同步系统。本发明是一种时间同步系统，其中时间主站，时间从站和管理节点经由多个网络连接，其特征在于，如果进行评估来切换发送时间分组的网络，则管理节点向时间从站报告能够识别要进行交换机的网络的信息。

10. 发明申请

WO2013078820A1 网元间的1588时间误差检测方法及装置审中-公开
公开(公告)号：WO2013078820A1
公开(公告)日：2013-06-06
申请号：PCT/CN2012/074297
申请日：2012-04-18
申请人：中兴通讯股份有限公司 , 徐健新 , 何力
发明人：徐健新 , 何力
IPC分类号： H04L12/26 , H04L12/24
CPC分类号： H04L7/0016 , H04J3/0667 , H04J3/14 , H04L41/064 , H04L43/106
摘要：本发明公开了一种网元间的1588时间误差检测方法及装置，上述方法包括：全网建立1588时间网络，网元间需要进行1588时间误差检测时，互相发送携带有本地时间戳的探测报文给对端网元；收到探测报文的网元根据预设的时间差算法，计算本地时间戳与上述探测报文中的时间戳的时间差，并根据上述时间差判断检测路径是否发生故障，检测路径发生故障时，上报告警。本发明防止了因时间误差导致时间的错误传递，确保了网络的稳定性。

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