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1. 发明申请

WO2013028849A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
公开(公告)号：WO2013028849A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052043
申请日：2012-08-23
申请人： RAMBUS INC. , PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
发明人： PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G11C7/10 , G06F13/14
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

2. 发明申请

WO2013028854A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
标题翻译：用于将外围功能映射到遗传存储器接口的方法和系统
公开(公告)号：WO2013028854A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052052
申请日：2012-08-23
申请人： Rambus Inc. , PEREGO, Richard, E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
发明人： PEREGO, Richard, E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G06F13/14 , G06F13/38 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
摘要翻译：存储器系统包括将命令和地址传送到主存储器模块的CPU。该模块包含一个缓冲电路，用于在CPU和主存储器之间中继命令和数据。存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持诸如图形处理等外围功能，以提高整体系统性能。缓冲电路有助于CPU和外设处理器之间的指令和数据通信，其方式可以最大限度地减少或消除修改CPU的需求，从而降低采用具有集成处理能力的主内存模块的实际障碍。

3. 发明申请

WO2013028859A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
公开(公告)号：WO2013028859A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052059
申请日：2012-08-23
申请人： Rambus Inc. , PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
发明人： PEREGO, Richard E. , BATRA, Pradeep , WOO, Steven , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G06F13/14 , G06F13/38 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

4. 发明申请

WO2013028827A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
标题翻译：将外部功能映射到记忆体界面的方法和系统
公开(公告)号：WO2013028827A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052000
申请日：2012-08-23
申请人： RAMBUS INC. , PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
发明人： PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
IPC分类号： G06F13/14 , G06F13/16 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
摘要翻译：存储器系统包括将命令和地址传送到主存储器模块的CPU。该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。

5. 发明申请

WO2015164049A1 MEMORY MIRRORING 审中-公开
标题翻译：记忆反射
公开(公告)号：WO2015164049A1
公开(公告)日：2015-10-29
申请号：PCT/US2015/024230
申请日：2015-04-03
申请人： RAMBUS, INC.
发明人： WOO, Steven , SECKER, David , KOLLIPARA, Ravindranath
IPC分类号： G06F12/00
CPC分类号： G06F11/1666
摘要： Memory system enabling memory mirroring in single write operations for primary and backup data storage. In one aspect, the system utilizes a memory channel including one or more latency groups, each encompassing memory modules that have the same signal timing to the controller. A primary and a backup copy of a data element can be written to two memory modules in the same latency group of the channel in a single write operation. In another aspect, a memory channel can store duplicate copies of data into multiple locations disposed in different memory modules and have different data propagation times. The relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay, such that a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.
摘要翻译：内存系统在单次写入操作中启用主镜像和备份数据存储的内存镜像。在一个方面，系统利用包括一个或多个等待时间组的存储器通道，每个延迟组包括与控制器具有相同信号定时的存储器模块。在单次写入操作中，数据元素的主要和备份副本可以写入通道的相同延迟组中的两个内存模块。在另一方面，存储器通道可以将重复的数据副本存储在设置在不同存储器模块中的多个位置，并具有不同的数据传播时间。根据数据传播延迟来调整多个位置之间的芯片选择，命令和地址信号的相对定时，使得数据元素可以响应于从存储器控制器发送的数据信号而写入多个位置传输事件。

6. 发明申请

WO2015127327A1 DISTRIBUTED PROCEDURE EXECUTION AND FILE SYSTEMS ON A MEMORY INTERFACE 审中-公开
标题翻译：分布式程序执行和存储器界面上的文件系统
公开(公告)号：WO2015127327A1
公开(公告)日：2015-08-27
申请号：PCT/US2015/016985
申请日：2015-02-21
申请人： RAMBUS INC.
发明人： WOO, Steven , PEREGO, Richard , BATRA, Pradeep , LAI, Lawrence , YEUNG, Chi-Ming
IPC分类号： G06F12/02 , G06F9/50 , G06F12/00
CPC分类号： G06F13/1694 , G06F12/0638
摘要： Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a DRAM memory channel. Nonvolatile memory residing on a DRAM memory channel may be integrated into the existing file system structures of operating systems. The nonvolatile memory residing on a DRAM memory channel may be presented as part or all of a distributed file system. Requests and/or remote procedure call (RPC) requests, or information associated with requests and/or RPCs, may be routed to the memory modules over the DRAM memory channel in order to service compute and/or distributed file system commands.
摘要翻译：非易失性存储器（例如，闪存，固态盘）被包括在DRAM存储器通道上的存储器模块上。驻留在DRAM存储器通道上的非易失性存储器可以被集成到操作系统的现有文件系统结构中。驻留在DRAM存储器通道上的非易失性存储器可以被呈现为分布式文件系统的一部分或全部。可以通过DRAM存储器通道将请求和/或远程过程调用（RPC）请求或与请求和/或RPC相关联的信息路由到存储器模块，以便为计算和/或分发的文件系统命令提供服务。

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