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1. 发明申请

WO0199162A3 GATE OXIDATION FOR VERTICAL TRENCH DEVICE 审中-公开
标题翻译：用于垂直倾斜装置的闸门氧化
公开(公告)号：WO0199162A3
公开(公告)日：2002-07-18
申请号：PCT/US0119882
申请日：2001-06-21
申请人： INFINEON TECHNOLOGIES CORP
发明人： MICHAELIS ALEXANDER , TEWS HELMUT HORST , KUDELKA STEPHAN , GRUENING ULRIKE , BEINTNER JOCHEN , SCHROEDER UWE
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/04 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28211 , H01L27/10864 , H01L27/10876 , H01L29/045 , H01L29/42368 , H01L29/518 , H01L29/66666 , H01L29/7827
摘要： A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a crystal plane sidewall (212) is used for the channel region, and crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.
摘要翻译：一种使用选择性蚀刻以在位于半导体衬底中的深沟槽的侧壁上提供期望的晶面取向的方法和由其形成的器件。优选地，在沟道区域中使用<100>晶面侧壁（212），并且在沟槽的拐角区域中使用<110>晶面（216）。然后可以执行栅极氧化，使得在角区域（222）中的氧化物比在沟槽的初级侧上的氧化物（218,220）上更厚，导致拐角区域与晶体管沟道/活性物质的自我隔离区域（224）。此外，该结构对有源区/深沟槽未对准相对不敏感。

2. 发明申请

WO0201607A3 METHOD OF PRODUCING TRENCH CAPACITOR BURIED STRAP 审中-公开
标题翻译：生产TRENCH电容器BURIED STRAP的方法
公开(公告)号：WO0201607A3
公开(公告)日：2002-05-23
申请号：PCT/US0120206
申请日：2001-06-25
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , BERGNER WOLFGANG , BRONNER GARY B , GRUENING ULRIKE , KUDELKA STEPHEN , MICHAELIS ALEXANDER , NESBIT LARRY , RADENS CARL J , SCHLOESSER TILL , TEWS HEOMUT HORST
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。绝缘材料沉积在存储电容器的节点导体（3）的上方。一层硅（9）沉积在阻挡材料上。将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

3. 发明申请

WO0141201A9 PROCESS FOR FABRICATING A UNIFORM GATE OXIDE OF A VERTICAL TRANSISTOR 审中-公开
标题翻译：制造垂直晶体管的均匀栅极氧化物的方法
公开(公告)号：WO0141201A9
公开(公告)日：2002-05-30
申请号：PCT/US0032471
申请日：2000-11-27
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： FALTERMEIER JOHNATHAN E , GRUENING ULRIKE , HEGDE SURYANARAYAN , JAMMY RAJARAO , LEE BRIAN S , TEWS HELMUT
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/04 , H01L29/12 , H01L29/423 , H01L29/78
CPC分类号： H01L21/28211 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10864 , H01L27/10876 , H01L29/045 , H01L29/4236 , H01L29/66666 , H01L29/7813 , H01L29/7827 , Y10S438/931
摘要： A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a (100) crystal plane and a (110) crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the (110) crystal plane of the trench side wall, but not into the (100) crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.
摘要翻译：一种用于制造垂直晶体管的栅极氧化物的工艺。在第一步骤中，在衬底中形成沟槽，沟槽从衬底的顶表面延伸并且具有沟槽底部和沟槽侧壁。沟槽侧壁包括（100）晶面和（110）晶面。接下来，在沟槽侧壁上形成均匀厚度的牺牲层。在形成牺牲层之后，通过牺牲层注入氮离子，使得氮离子注入到沟槽侧壁的（110）晶面中，但不注入沟槽侧壁的（100）晶面。然后去除牺牲层，并且沟槽侧壁被氧化以形成栅极氧化物。

4. 发明申请

WO0199158A2 COLLAR FORMATION BY SELECTIVE OXIDE DEPOSITION 审中-公开
标题翻译：通过选择性氧化物沉积形成的组合
公开(公告)号：WO0199158A2
公开(公告)日：2001-12-27
申请号：PCT/US0119578
申请日：2001-06-19
申请人： INFINEON TECHNOLOGIES CORP
发明人： BEINTNER JOCHEN , MICHAELIS ALEXANDER , GRUENING ULRIKE , SPINDLER OSWALD , GABRIC ZVONIMIR
IPC分类号： H01L21/316 , H01L21/32 , H01L21/8242 , H01L21/00
CPC分类号： H01L27/10861 , H01L21/31612 , H01L21/32 , H01L27/1087
摘要： A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench (104) in a silicon substrate (102), and depositing and recessing a nitride liner (112) in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide (116) is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar (116) in the trench.
摘要翻译：根据本发明的在沟槽中形成氧化物环的方法包括在硅衬底（102）中形成沟槽（104），以及沉积和凹入沟槽中的氮化物衬垫（112）以暴露部分的硅衬底在沟槽的侧壁上。对硅衬底的部分上的氮化物衬垫选择性地沉积氧化物（116）。从氮化物衬垫的表面去除残余氧化物，以在沟槽中形成套环（116）。

5. 发明申请

WO0126139A3 DRAM BIT LINES AND SUPPORT CIRCUITRY CONTACTING SCHEME 审中-公开
标题翻译： DRAM位线和支持电路联系方案
公开(公告)号：WO0126139A3
公开(公告)日：2001-10-18
申请号：PCT/US0027216
申请日：2000-10-02
申请人： INFINEON TECHNOLOGIES CORP
发明人： SCHNABEL RAINER FLORIAN , GRUENING ULRIKE , RUPP THOMAS , MUELLER GERHARD
IPC分类号： G11C5/06 , G11C7/18 , G11C11/4097 , H01L21/285 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10885 , G11C5/063 , G11C7/18 , G11C11/4097 , H01L21/28525 , H01L21/76807 , H01L21/76897 , H01L27/105 , H01L27/10888 , H01L27/10894
摘要： A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention, includes forming gate structures (204) for transistors in an array region (212) and a support region (214) of a substrate (202). First contacts (222) are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts (232) are formed between first level bitlines (234) in the array region and a first portion of the first contacts, while forming second contacts (236 and 260) to a first metal layer (233, 264) from the gate structures (204) and diffusion regions (262) in the support region. Third contacts (246) are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer (251, 268) from the first metal layer in the support region.
摘要翻译：根据本发明，制造具有由三个接触电平构成的分裂电平折叠位线结构的半导体存储器的方法包括：在阵列区域（212）和支撑区域（214）中形成用于晶体管的栅极结构（204）的衬底（202）。第一触点（222）形成在阵列区域中的栅极结构之间的扩散区域。第一触点具有与阵列区域中的所有第一触点基本相同的高度。第二触点（232）形成在阵列区域中的第一级位线（234）和第一触点的第一部分之间，同时从栅极结构形成第二触点（236和260）到第一金属层（233,264）（204）和扩散区（262）。第三触点（246）形成在阵列区域中的第二电平位线和第一触点的第二部分之间，同时从支撑区域中的第一金属层形成第三触点到第二金属层（251,268）。

6. 发明申请

WO0245130A3 EMBEDDED VERTICAL DRAM CELLS AND DUAL WORKFUNCTION LOGIC GATES 审中-公开
标题翻译：嵌入式垂直DRAM电池和双功能逻辑门
公开(公告)号：WO0245130A3
公开(公告)日：2004-01-08
申请号：PCT/US0144625
申请日：2001-11-28
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： GRUENING ULRIKE , DIVAKARUNI RAMACHANDRA , MANDELMAN JACK , RUPP THOMAS
IPC分类号： H01L27/10 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10864 , H01L27/10885 , H01L27/10891
摘要： A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.
摘要翻译：一种用于生产非常高密度的嵌入式DRAM /非常高性能的逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元，包括：在硅衬底中形成法兰电容器，栅极氧化物层，多晶硅层和沉积在其上的顶部侧面氮化物层; 在阵列和支撑区域上施加图案化掩模并在氮化物层，多晶硅层和浅沟槽隔离区域中形成凹陷; 在氮化物层，多晶硅层和浅沟槽隔离区域的凹槽中形成硅化物和氧化物盖; 施加阻挡掩模以保护支撑物，同时从阵列剥离氮化物层并将暴露的多晶硅层蚀刻到栅极氧化物层的顶部; 从支撑区域剥离氮化物层并在阵列和支撑区域上沉积多晶硅层; 应用掩模来图案化并在阵列中形成位线扩散螺柱着陆焊盘，并在支撑晶体管上形成栅极导体; 打击着陆板和门导体的顶部; 施加层间氧化层，然后在层间氧化层中开通通孔，以建立导电布线通道。

7. 发明申请

WO0247116A8 STRUCTURE AND METHOD FOR FORMING A BODY CONTACT FOR VERTICAL TRANSISTOR CELLS 审中-公开
标题翻译：用于形成垂直晶体管细胞的身体接触的结构和方法
公开(公告)号：WO0247116A8
公开(公告)日：2003-12-04
申请号：PCT/US0144624
申请日：2001-11-28
申请人： INFINEON TECHNOLOGIES CORP
发明人： GRUENING ULRIKE , KLOSE HELMUT , BERGNER WOLFGANG
IPC分类号： H01L21/8242 , H01L
CPC分类号： H01L27/10867

8. 发明申请

WO0201567A3 STRUCTURE AND PROCESS FOR 6F<2> TRENCH CAPACITOR DRAM CELL WITH VERTICAL MOSFET AND 3F BITLINE PITCH 审中-公开
标题翻译：具有垂直MOSFET和3F位线点的6F 2晶体管电容器DRAM单元的结构和工艺
公开(公告)号：WO0201567A3
公开(公告)日：2002-02-25
申请号：PCT/US0120221
申请日：2001-06-25
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： MANDELMAN JACK A , DIVAKARUNI RAMACHANDRA , RADENS CARL J , GRUENING ULRIKE
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841

9. 发明申请

WO0227797A3 SHALLOW TRENCH TRANSISTOR DEEP TRENCH CAPACITOR MEMORY CELL 审中-公开
标题翻译：低压透镜晶体管深度TRENCH电容器存储单元
公开(公告)号：WO0227797A3
公开(公告)日：2003-01-09
申请号：PCT/US0127074
申请日：2001-08-30
申请人： INFINEON TECHNOLOGIES CORP
发明人： ALSMEIER JOHANN , GRUENING ULRIKE
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10861
摘要： An improved sub 8F memory cell is disclosed. The sub 8F cell includes a trench capacitor (260) formed in a substrate; a shallow transistor trench (STT) (287) formed in the substrate; a transistor comprising a first diffusion region (213), the first diffusion region couples the transistor to the gate, a second diffusion region (214), the second diffusion region couples the transistor to a bit line, and a gate (212) serving as a word line, the gate includes a buried portion and a non-buried portion, wherein the buried portion of the gate occupies the shallow transistor trench.
摘要翻译：公开了改进的子8F 2存储器单元。子8F 2单元包括形成在衬底中的沟槽电容器（260）形成在衬底中的浅晶体管沟槽（STT）（287）; 晶体管，包括第一扩散区域（213），第一扩散区域将晶体管耦合到栅极，第二扩散区域（214），第二扩散区域将晶体管耦合到位线，以及栅极（212）一个字线，该栅极包括一个埋入部分和一个非埋置部分，其中栅极的埋入部分占据浅晶体管沟槽。

10. 发明申请

WO0189284A3 TRENCH CAPACITOR WITH INSULATION COLLAR STACK, AND METHOD OF FORMING THEREOF 审中-公开
标题翻译：具有绝缘胶卷的TRENCH电容器及其形成方法
公开(公告)号：WO0189284A3
公开(公告)日：2002-05-30
申请号：PCT/US0115896
申请日：2001-05-16
申请人： INFINEON TECHNOLOGIES CORP
发明人： TEWS HELMUT HORST , MICHAELIS ALEXANDER , KUDELKA STEPHEN , SCHROEDER UWE , GRUENING ULRIKE
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： A method of using at least two insulative layers to form the isolation collar of a trench capacitor, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.
摘要翻译：使用至少两个绝缘层形成沟槽电容器的隔离环的方法，以及由其形成的器件。第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。优选地，TEOS工艺和LOCOS工艺都用于形成第一层。第二层优选是形成在氧化物层上的氮化硅层（114）。多层用作沟槽的隔离环叠层。第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

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