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1. 发明申请

WO0201607A3 METHOD OF PRODUCING TRENCH CAPACITOR BURIED STRAP 审中-公开
标题翻译：生产TRENCH电容器BURIED STRAP的方法
公开(公告)号：WO0201607A3
公开(公告)日：2002-05-23
申请号：PCT/US0120206
申请日：2001-06-25
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： DIVAKARUNI RAMACHANDRA , MANDELMAN JACK A , BERGNER WOLFGANG , BRONNER GARY B , GRUENING ULRIKE , KUDELKA STEPHEN , MICHAELIS ALEXANDER , NESBIT LARRY , RADENS CARL J , SCHLOESSER TILL , TEWS HEOMUT HORST
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。绝缘材料沉积在存储电容器的节点导体（3）的上方。一层硅（9）沉积在阻挡材料上。将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

2. 发明申请

WO0189284A3 TRENCH CAPACITOR WITH INSULATION COLLAR STACK, AND METHOD OF FORMING THEREOF 审中-公开
标题翻译：具有绝缘胶卷的TRENCH电容器及其形成方法
公开(公告)号：WO0189284A3
公开(公告)日：2002-05-30
申请号：PCT/US0115896
申请日：2001-05-16
申请人： INFINEON TECHNOLOGIES CORP
发明人： TEWS HELMUT HORST , MICHAELIS ALEXANDER , KUDELKA STEPHEN , SCHROEDER UWE , GRUENING ULRIKE
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： A method of using at least two insulative layers to form the isolation collar of a trench capacitor, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.
摘要翻译：使用至少两个绝缘层形成沟槽电容器的隔离环的方法，以及由其形成的器件。第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。优选地，TEOS工艺和LOCOS工艺都用于形成第一层。第二层优选是形成在氧化物层上的氮化硅层（114）。多层用作沟槽的隔离环叠层。第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

3. 发明申请

WO0191180A3 SYSTEM AND METHOD OF FORMING A VERTICALLY ORIENTED DEVICE IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中形成垂直方向的器件的系统和方法
公开(公告)号：WO0191180A3
公开(公告)日：2002-07-18
申请号：PCT/US0115757
申请日：2001-05-15
申请人： INFINEON TECHNOLOGIES CORP
发明人： TEWS HELMUT HORST , LEE BRIAN S , MICHAELIS ALEXANDER , SCHROEDER UWE , KUDELKA STEPHEN
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L21/768 , H01L21/02
CPC分类号： H01L27/10864 , H01L21/76237 , H01L21/823487 , H01L27/10841 , H01L27/10867
摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.
摘要翻译：使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分沟槽暴露进一步加工。或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

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