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1. 发明申请

WO2008058903A1 VERTICAL DRAM DEVICE, HAVING A TRENCH CAPACITOR AND A VERTICAL TRANSISTOR, AND MANUFACTURING METHOD 审中-公开
标题翻译：具有TRENCH电容器和垂直晶体管的垂直DRAM器件，以及制造方法
公开(公告)号：WO2008058903A1
公开(公告)日：2008-05-22
申请号：PCT/EP2007/062115
申请日：2007-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHENG, Kangguo , HENRY, Richard, Oneil , SETTLEMYER JR, Kenneth
发明人： CHENG, Kangguo , HENRY, Richard, Oneil , SETTLEMYER JR, Kenneth
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/306 , H01L29/78
CPC分类号： H01L21/32134 , H01L21/30608 , H01L27/10841 , H01L27/10864
摘要： A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor (22) for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor (20). The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill (22) of the capacitor to form exposed regions of single-crystal semiconductor (28 "a) on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer (34') is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer (38'), wherein the trench top insulating layer extends below the vertical gate insulating layer.
摘要翻译：一种形成垂直DRAM装置的方法。下沟槽填充有用于电容器的多晶或非晶半导体（22）。上沟槽部分具有单晶半导体（20）的暴露的侧壁。该方法然后包括蚀刻单晶半导体侧壁以将上沟槽部分加宽超过电容器的半导体填充物（22）的暴露的上表面，以在底部部分上形成单晶半导体（28“a）的暴露区域沟槽顶部绝缘层（34'）沉积在上部沟槽的底部上，在半导体填充物的上表面上方并且在相邻的单个区域上方沉积该方法然后包括形成垂直栅极电介质层（38'），其中沟槽顶部绝缘层在垂直栅极绝缘层下方延伸。

2. 发明申请

WO2005064672A2 INTEGRATED CIRCUIT MEMORY CELLS AND METHODS OF FORMING 审中-公开
标题翻译：集成电路记忆细胞和形成方法
公开(公告)号：WO2005064672A2
公开(公告)日：2005-07-14
申请号：PCT/US2004/042245
申请日：2004-12-15
申请人： MICRON TECHNOLOGY, INC. , PATERSON, Alexander
发明人： PATERSON, Alexander
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/1203 , H01L28/60
摘要： An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The second source/drain may be included in a digit line inner conductor connecting a digit line to a transistor channel of the vertical transistor. The channel may include a semiconductive upward extension of the combined first electrode and first source/drain. The memory cell may be included in an array of a plurality of such memory cells wherein the second electrode is a common electrode among the plurality. The memory cell may provide a straight-line conductive path between the first electrode and a digit line, the path extending through the vertical transistor.
摘要翻译：集成电路存储单元包括组合的第一电容器电极和第一晶体管源极/漏极，第二电容器电极，第一和第二电极之间的电容器电介质，以及在第一源极/漏极之上并包括第一源极/漏极的垂直晶体管。第二源极/漏极可以包括在将数字线连接到垂直晶体管的晶体管沟道的数字线内部导体中。通道可以包括组合的第一电极和第一源极/漏极的半导体向上延伸。存储单元可以包括在多个这样的存储单元的阵列中，其中第二电极是多个中的公共电极。存储器单元可以在第一电极和数字线之间提供直线导电路径，该路径延伸穿过垂直晶体管。

3. 发明申请

WO2005020318A1 SELF-ALIGNED DRAIN/CHANNEL JUNCTION IN VERTICAL PASS TRANSISTOR DRAM CELL DESIGN FOR DEVICE SCALING 审中-公开
标题翻译：用于设备放大的垂直通用晶体管DRAM单元设计中的自对准漏极/通道结
公开(公告)号：WO2005020318A1
公开(公告)日：2005-03-03
申请号：PCT/US2004/026058
申请日：2004-08-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , WANG, Geng , MCSTAY, Kevin , WEYBRIGHT, Mary, Elizabeth , LI, Yujun , CHIDAMBARRAO, Dureseti
发明人： WANG, Geng , MCSTAY, Kevin , WEYBRIGHT, Mary, Elizabeth , LI, Yujun , CHIDAMBARRAO, Dureseti
IPC分类号： H01L21/8234
CPC分类号： H01L27/10876 , H01L21/26586 , H01L27/10864 , H01L29/1041 , H01L29/66537 , H01L29/66666 , H01L29/7827 , H01L29/945
摘要： A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle θ + δ with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle θ with respect to vertical of a dopant into the channel below the source region.
摘要翻译：提供了形成深沟槽垂直晶体管的方法。在掺杂半导体衬底中形成具有侧壁的深沟槽。半导体衬底在其表面中包括反向漏极区域和沿着侧壁的通道。漏极区域具有顶层和底层。反向掺杂的源极区域形成在与通道下方的侧壁并置的衬底中。栅极氧化层形成在与栅极导体并置的沟槽的侧壁上。执行将栅极导体凹入低于漏极区域的底部电平的步骤，然后相对于反向掺杂物的垂直角进行成角度的离子注入进入源极区域下方的沟道，并以一定角度进行成角度的离子注入相对于掺杂剂的垂直方向在源极区域下方的沟道中。

4. 发明申请

WO2004030028A3 METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR CIRCUIT 审中-公开
标题翻译：生产集成半导体电路的方法
公开(公告)号：WO2004030028A3
公开(公告)日：2004-06-03
申请号：PCT/DE0303068
申请日：2003-09-16
申请人： INFINEON TECHNOLOGIES AG , GOEBEL BERND , MOLL PETER , SCHUMANN DIRK , SEIDL HARALD
发明人： GOEBEL BERND , MOLL PETER , SCHUMANN DIRK , SEIDL HARALD
IPC分类号： H01L20060101 , H01L21/768 , H01L21/8239 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10888 , H01L21/76895 , H01L27/10864 , H01L27/10894
摘要： The invention relates to a method for the production of an integrated semiconductor circuit, whereby electrical contacts (20), for first conducting structures (1), are produced in the memory region (I) and the first conducting structures (1) are contacted, without contacting second conducting structures (2) arranged laterally with respect to the first conducting structures (1), which laterally border the first conducting structures (1) or are arranged too close to the same to be selectively lithographically masked. According to the invention, the first conducting structures (1) are contacted, whereby a conducting layer (L) is deposited and structured after a planarisation in the memory region at the level of the first conducting structures (1) above the second conducting structures (2), which is applied in the logic region for the generation of gate electrodes, for example. Intermediate contacts (10) are thus structured which are so wide that contact holes for the electrical contacts can be fitted thereon. The deposition of a nitride layer for the protection of the second conducting layer (2) is thus superfluous.
摘要翻译：本发明涉及一种用于制造在其中为第一导电结构（1）的存储器区域（I）（20）制备的半导体集成电路的电接触，并且所述第一导电结构（1）由所述第一结构没有横向导电接触（2）（1）设置在第二导电图案，以接触施加于第一导电图案的侧面（1）抵接或挨着它们紧密地布置成选择性地掩蔽以它们能够光刻。根据本发明，第一导电结构（1）由所述存储区域在已经在所述逻辑区域被使用过的第二导电结构（2）平坦化，导电层（L）后上面的第一导电结构（1）的电平相接触，例如用于生产栅电极的变得分离和结构化。这个中间触点（10）是结构化的，其宽度足以使电触点（20）的触点孔可以调节到它们。不需要沉积氮化物层以保护第二导电结构（2）。

5. 发明申请

WO03005447A8 STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开
标题翻译：嵌入式BITLINE和POLYSILICON INTERCONNECT嵌入垂直DRAM阵列的结构与方法
公开(公告)号：WO03005447A8
公开(公告)日：2004-02-19
申请号：PCT/GB0202961
申请日：2002-06-27
申请人： IBM , IBM UK , INFINEON TECHNOLOGIES AG
发明人： DIVAKARUNI RAMACHANDRA , GRUENING ULRIKE , MANDELMAN JACK , NESBIT LARRY , RADENS CARL
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。该工艺消除了对M0金属化层的需要。

6. 发明申请

WO2003060994A1 SPEICHERZELLE MIT NIEDERTEMPERATUR-SCHICHTEN IM GRABENKONDENSATOR 审中-公开
标题翻译：和坟墓电容低温度LAYERS MEMORY CELL
公开(公告)号：WO2003060994A1
公开(公告)日：2003-07-24
申请号：PCT/EP2003/000088
申请日：2003-01-08
申请人： INFINEON TECHNOLOGIES AG , TEMMLER, Dietmar , GUTSCHE, Martin , POPP, Martin , SEIDL, Harald
发明人： TEMMLER, Dietmar , GUTSCHE, Martin , POPP, Martin , SEIDL, Harald
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867 , H01L27/10832 , H01L27/10864
摘要： Es werden Speicherzellen mit Grabenkondensatoren beschrieben, wobei der Grabenkondensator mit einem Material mindestens teilweise aufgefüllt ist, das Hochtemperaturprozesse, die bei der Herstellung eines Speicherbausteins verwendet werden, nicht ohne Beeinträchtigung ihrer elektrischen Parameter überstehen könnte. Erfindungswesentlich ist, dass das Material des Grabenkondensators erst nach den Hochtemperaturprozessen in den Graben eingebracht wird. Durch das erfindungsgemäße Verfahren können dielektrische Schichten mit großen Dielektrizitätskonstanten und Elektrodenschichten aus metallischem Material verwendet werden. Somit werden die elektrischen Eigenschaften des Grabenkondensators gegenüber bekannten Grabenkondensatoren verbessert.
摘要翻译：它将与严重电容器的存储单元，其中，所述电容器严重填充有材料至少部分地，这是在制造存储器芯片的所用的高温工艺，不能在不影响它们的电参数生存进行说明。本发明的特征在于，所述严重电容器的材料仅在沟槽中的高温工艺之后引入。本发明的方法的介电层可以用金属材料制成的大介电常数和电极层一起使用。因此，严重的电容器的电特性得以改善相对于已知的严重电容器。

7. 发明申请

WO2003017356A2 IMPROVED STRAP RESISTANCE USING SELECTIVE OXIDATION TO CAP DT POLY BEFORE STI ETCH 审中-公开
标题翻译：使用选择性氧化改善纹理电阻，以便在涂层之前进行CAP DT聚合
公开(公告)号：WO2003017356A2
公开(公告)日：2003-02-27
申请号：PCT/EP2002/009009
申请日：2002-08-12
申请人： INFINEON TECHNOLOGIES AG
发明人： WENSLEY, Paul , COMMONS, Martin , MONO, Tobias , KLEE, Veit
IPC分类号： H01L21/762
CPC分类号： H01L27/10864 , H01L21/76224 , H01L21/763 , H01L27/10861
摘要： A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.
摘要翻译：一种为半导体晶片（100）提供浅沟槽（143）隔离的方法。沟槽（113）形成在第一半导体材料（112）和衬垫氮化物（114）内，在沟槽（113）之间的区域中留下第一半导体材料（112）的一部分和衬垫氮化物（114）。第二半导体材料（116）沉积在沟槽（113）上以将沟槽（113）填充到第一半导体材料（112）顶表面下方的高度。在第二半导体材料（116）上有选择地形成第一绝缘体（130）。去除衬垫氮化物（114）和沟槽（113）之间的第一半导体材料（112）的一部分以隔离晶片（100）的元件区域并形成具有低电阻的带（142）。

8. 发明申请

WO03017331A2 MEMORY CELL WITH A TRENCH CAPACITOR AND VERTICAL SELECTION TRANSISTOR AND ANNULAR CONTACTING AREA FORMED BETWEEN THEM 审中-公开
标题翻译： CAPACITOR WITH抓取和垂直选择晶体管和这些成型环形接触之间的存储器CELL
公开(公告)号：WO03017331A2
公开(公告)日：2003-02-27
申请号：PCT/DE0202559
申请日：2002-07-12
申请人： INFINEON TECHNOLOGIES AG , BIRNER ALBERT , GOLDBACH MATTHIAS , SCHLOESSER TILL
发明人： BIRNER ALBERT , GOLDBACH MATTHIAS , SCHLOESSER TILL
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/00
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876
摘要： The top capacitor electrode (10) of the trench capacitor is connected to an epitactically grown source/drain area (21) of the selection transistor (20) by an annular, monocrystalline Si contacting area (7.1). The gate electrode layer (24) has an oval peripheral course around the transistor (20), wherein the oval peripheral courses of the gate electrode layers (24) form overlapping areas (24.3) of memory cells placed in rows next to one another along a word line in order to enhance packing density.
摘要翻译：坟墓电容器的上电容器电极（10）由连接到外延生长的源的管状单晶Si接触区域（7.1）形成/漏极选择晶体管（20）的区域（21）。栅电极层（24）具有的晶体管（20）围绕椭圆周过程中，形成沿着存储器单元的字线，以增加重叠区域（24.3）的填充密度排成一列的栅电极层（24）的椭圆形的圆周轮廓。

9. 发明申请

WO02073694A3 MEMORY CELL COMPRISING A TRENCH AND METHOD FOR PRODUCTION THEREOF 审中-公开
标题翻译：根据上述制造的沟槽和方法MEMORY CELL
公开(公告)号：WO02073694A3
公开(公告)日：2003-02-06
申请号：PCT/DE0200596
申请日：2002-02-19
申请人： INFINEON TECHNOLOGIES AG , SCHREMS MARTIN , WEIS ROLF
发明人： SCHREMS MARTIN , WEIS ROLF
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/10891
摘要： The invention relates to a memory cell (1), comprising a trench (3), in which a trench capacitor is arranged. Furthermore a vertical transistor is formed in the trench (3), above the trench capacitor. A barrier layer (60) is provided for the electrical connection of the conducting trench filling (10) to a lower doped region (18) of the vertical transistor. The barrier layer (60) is a diffusion barrier for doped material or impurities contained in the conducting trench filling.
摘要翻译：本发明涉及具有沟槽（3）的存储单元（1），其中电容器被布置严重。此外，在沟槽（3）的严重电容器之上的垂直晶体管形成。对于导电严重填充（10）到所述垂直晶体管的下部掺杂区（18）的电连接，阻挡层（60）被布置。阻挡层（60）是扩散阻挡层以包含在导电严重填充掺杂剂或杂质。

10. 发明申请

WO03005447A2 STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开
标题翻译：硅化双线和多晶硅互连嵌入式垂直DRAM阵列的结构和制作方法
公开(公告)号：WO03005447A2
公开(公告)日：2003-01-16
申请号：PCT/GB0202961
申请日：2002-06-27
申请人： IBM , IBM UK , INFINEON TECHNOLOGIES AG
发明人： DIVAKARUNI RAMACHANDRA , GRUENING ULRIKE , MANDELMAN JACK , NESBIT LARRY , RADENS CARL
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。该工艺消除了对M0金属化层的需求。

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