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1. 发明申请

WO1996024105A1 TERMINAL FOR DISTRIBUTING ELECTRONIC INFORMATION 审中-公开
标题翻译：分配电子信息终端
公开(公告)号：WO1996024105A1
公开(公告)日：1996-08-08
申请号：PCT/JP1995002176
申请日：1995-10-23
申请人： HITACHI, LTD. , TAKASE, Satoshi , KUBO, Masaharu , MUNAKATA, Takeshi
发明人： HITACHI, LTD.
IPC分类号： G06F17/60
CPC分类号： G07F11/002 , G06K17/00 , G06Q10/10 , G06Q20/123 , G06Q20/18 , G07F17/0014
摘要： An electronic information distributing terminal (2A) which distributes electronic information including document information and the moving image information corresponding to the document information by storing the electronic information on a memory card (1) provided with an electrically rewritable nonvolatile semiconductor storage device. The terminal (2A) has a card stock (225) prepared by storing information transmitted through a communication interface (200) for electronic information to be distributed on a plurality of memory cards and distributes the electronic information by ejecting the memory cards even in response to a request of distributing only the electronic information and, at the same time, uses the memory card inserted together with the request as an added card stock (225). Therefore, the distribution service of such electronic information is efficient.
摘要翻译：一种电子信息分配终端（2A），其通过将电子信息存储在具有电可重写的非易失性半导体存储装置的存储卡（1）上，分发包括文档信息的电子信息和与文档信息相对应的运动图像信息。终端（2A）具有通过存储通过通信接口（200）发送的用于分配在多个存储卡上的电子信息的信息而准备的卡片（225），并且通过弹出存储卡来分发电子信息，即使响应于仅分发电子信息的请求，并且同时使用与请求一起插入的存储卡作为附加的卡片（225）。因此，这种电子信息的分发服务是有效的。

2. 发明申请

WO1999023696A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME______ 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO1999023696A1
公开(公告)日：1999-05-14
申请号：PCT/JP1997003969
申请日：1997-10-30
申请人： HITACHI, LTD. , MIYAMOTO, Toshio , ANJO, Ichiro , ARITA, Junichi , EGUCHI, Shuji , KITANO, Makoto , KUBO, Masaharu , MUNAKATA, Takeshi , FUKUDA, Takuya
发明人： HITACHI, LTD.
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/4985 , H01L23/49894 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02333 , H01L2224/0235 , H01L2224/02351 , H01L2224/02377 , H01L2224/0401 , H01L2224/05548 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13024 , H01L2224/1308 , H01L2224/13099 , H01L2224/13144 , H01L2224/274 , H01L2224/45144 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/00
摘要： In a chip-size package, a low-elasticity elastomer (2) which relieves and absorbs the stresses concentrated upon bump electrodes (5) is formed on the main surface of a semiconductor chip (1), and the wiring (4) connected to bonding pads (7) is led out to the upper surface of the elastomer (2) by way of through holes formed through the elastomer (2) and connected to the bump electrodes (5). The stresses concentrated upon the bump electrodes (5) are absorbed and relieved by not only the elastomer (2), but also the expansion and contraction of the wiring (4) led out to the upper surface of the elastomer (2) by laying the wiring (4) in a curved pattern.
摘要翻译：在芯片尺寸封装中，在半导体芯片（1）的主表面上形成缓冲和吸收集中在凸块电极（5）上的应力的低弹性弹性体（2），并且连接到接合焊盘（7）通过穿过弹性体（2）形成的通孔并连接到凸块电极（5）被引出到弹性体（2）的上表面。集中在凸块电极（5）上的应力不仅通过弹性体（2）而被吸收和释放，而且通过将弹性体（2）的上表面引出到弹性体（2）的膨胀和收缩布线（4）呈弧形图案。

3. 发明申请

WO1998025305A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO1998025305A1
公开(公告)日：1998-06-11
申请号：PCT/JP1996003547
申请日：1996-12-04
申请人： HITACHI, LTD. , MIYAMOTO, Toshio , NISHIMURA, Asao , NOGUCHI, Koki , MICHISHITA, Satoshi , HORIGUCHI, Masashi , KUBO, Masaharu
发明人： HITACHI, LTD.
IPC分类号： H01L25/11
CPC分类号： H01L25/18 , H01L23/4985 , H01L25/0657 , H01L25/105 , H01L2224/16 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2225/1029 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/01019 , H01L2924/01021 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor process for a laminated package that contains a semiconductor chip on which at least a CPU and flash memory are formed and one or more semiconductor chips on which at least DRAMs are formed. The process comprises the steps of: patterning conductive layers formed on the tape carriers so that leads may protrude into device holes on one side and connected to the through holes in tape carriers on the other side; sealing the semiconductor chips with a resin after the leads are bonded to the terminals of the chips for electrical connections; stacking the tape carriers with their through holes aligned and filling conductor in the through holes for electrical connections; and forming external terminals connected with the through holes on one end.
摘要翻译：一种用于层压封装的半导体工艺，其包含至少形成有CPU和闪速存储器的半导体芯片和至少形成有DRAM的一个或多个半导体芯片。该方法包括以下步骤：对形成在带状载体上的导电层进行构图，使得引线可以突出到一侧的器件孔中，并与另一侧的带状载体中的通孔连接; 在将引线接合到用于电连接的芯片的端子之后，用树脂密封半导体芯片; 堆叠磁带载体，其通孔对准，并将导体填充在通孔中用于电连接; 并在一端形成与通孔连接的外部端子。

4. 发明申请

WO1998025213A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO1998025213A1
公开(公告)日：1998-06-11
申请号：PCT/JP1996003550
申请日：1996-12-04
申请人： HITACHI, LTD. , NOGUCHI, Koki , MICHISHITA, Satoshi , HORIGUCHI, Masashi , KUBO, Masaharu , MIYAMOTO, Toshio , NISHIMURA, Asao
发明人： HITACHI, LTD.
IPC分类号： G06F15/78
CPC分类号： G11C5/06 , G06F13/4239 , G06F15/7842 , G11C5/04 , H01L2224/50
摘要： A semiconductor integrated circuit device having a package structure, in which two kinds of chips, one chip mounted with a CPU and a flash memory and the other mounted with a DRAM are contained in a single package. This structure reduces the number of external connection terminals and the IC mounting area, and lowers the manufacturing cost. The semiconductor integrated circuit device comprises a chip (MF) mounted with a microcomputer including a CPU, a memory and peripheral circuits and a flash memory, and a chip (AD) mounted with a DRAM and a logic circuit such as an ASIC. In the connection between the chip (MF) and the other chip (AD), address terminals (A0-A10), data input/output terminals (D0-D31), a power supply terminal (Vcc), a ground terminal (Vss) and control terminals such as row address strobe terminals ( RAS , column address strobe terminal CASL , CASH , CASHL , CASHH ) are connected to the same external connection terminals of the single-package semiconductor integrated circuit.
摘要翻译：具有封装结构的半导体集成电路器件被包含在单个封装中，其中两种芯片，安装有CPU和闪存的一个芯片以及另一个安装有DRAM的芯片。该结构减少了外部连接端子和IC安装面积的数量，降低了制造成本。半导体集成电路装置包括安装有包括CPU，存储器和外围电路和闪速存储器的微计算机的芯片（MF）以及安装有DRAM和诸如ASIC的逻辑电路的芯片（AD）。在芯片（MF）和另一个芯片（AD）之间的连接中，地址端子（A0-A10），数据输入/输出端子（D0-D31），电源端子（Vcc），接地端子（Vss）以及诸如行地址选通端子（“RAS”，“列地址选通端子”，“CASL”，“CASH”，“CASHL”，“ 连接到单封装半导体集成电路的相同的外部连接端子。

5. 发明申请

WO1998025304A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO1998025304A1
公开(公告)日：1998-06-11
申请号：PCT/JP1996003549
申请日：1996-12-04
申请人： HITACHI, LTD. , MIYAMOTO, Toshio , NISHIMURA, Asao , NOGUCHI, Koki , MICHISHITA, Satoshi , HORIGUCHI, Masashi , KUBO, Masaharu , SHIBA, Kazuyoshi
发明人： HITACHI, LTD.
IPC分类号： H01L25/065
CPC分类号： H01L23/49816 , H01L23/49572 , H01L25/0657 , H01L25/105 , H01L27/10814 , H01L27/10894 , H01L27/118 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2225/1029 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01019 , H01L2924/01021 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/13091 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H01L2924/3511 , H01L2224/0401
摘要： A multilayered package in which a plurality of tape carriers where semiconductor chips are mounted are stacked. One end of each of leads formed on one side of each tape carrier is electrically connected to one of the connecting terminals of the semiconductor chips, and the other end of each of the leads are electrically connected to one of the through holes made in the carriers. The connecting terminals which are common to the semiconductor chips are formed at an area of the carriers and led to the external connecting terminals through the through holes.
摘要翻译：堆叠安装半导体芯片的多个带载体的多层封装。形成在每个带载体的一侧上的每个引线的一端电连接到半导体芯片的一个连接端子，并且每个引线的另一端电连接到在载体中形成的通孔之一。半导体芯片共用的连接端子形成在载体的区域并通过通孔导向外部连接端子。

6. 发明申请

WO1998025271A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO1998025271A1
公开(公告)日：1998-06-11
申请号：PCT/JP1996003548
申请日：1996-12-04
申请人： HITACHI, LTD. , NOGUCHI, Koki , MICHISHITA, Satoshi , HORIGUCHI, Masashi , KUBO, Masaharu , MIYAMOTO, Toshio , NISHIMURA, Asao
发明人： HITACHI, LTD.
IPC分类号： G11C11/407
CPC分类号： G11C11/409 , G11C11/406
摘要： A semiconductor integrated circuit device for high-speed data transfer, wherein wait control is eliminated to allow a logic circuit to access a DRAM during the self-refreshing period of the DRAM. The integrated circuit comprises a chip that includes a microcomputer incorporated with a CPU, memories and peripheral circuits, and a flash memory; and another chip that includes DRAMs and a logic circuit, such as an ASIC. The control of the DRAM depends on whether the DRAM is in the normal access period or in the self-refreshing period. In the DRAM self-refreshing period, the refreshing operations are canceled so that the logic circuit can access the DRAM when the logic circuit requests the access to the DRAM by using readout/write signals R/W.
摘要翻译：一种用于高速数据传输的半导体集成电路装置，其中消除了等待控制，以允许逻辑电路在DRAM的自刷新周期期间存取DRAM。集成电路包括芯片，其包括与CPU结合的微计算机，存储器和外围电路以及闪速存储器; 以及包括DRAM和诸如ASIC的逻辑电路的另一芯片。 DRAM的控制取决于DRAM是处于正常访问周期还是在自刷新期间。在DRAM自刷新周期中，刷新操作被取消，使得当逻辑电路通过使用读出/写入信号R / W请求访问DRAM时逻辑电路可以访问DRAM。

7. 发明申请

WO1998018257A1 CCD CAMERA DEVICE 审中-公开
标题翻译： CCD相机设备
公开(公告)号：WO1998018257A1
公开(公告)日：1998-04-30
申请号：PCT/JP1996003041
申请日：1996-10-21
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD. , HITACHI DEVICE ENGINEERING, CO., LTD. , TAKASE, Satoshi , TAKAHASHI, Takashi , OSADA, Tomoki , ODAKA, Teruaki , TAKAGISHI, Hiroaki
发明人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD. , HITACHI DEVICE ENGINEERING, CO., LTD.
IPC分类号： H04N05/335
CPC分类号： H04N9/44 , H04N9/045
摘要： A CCD camera, in which video signals are obtained by operating a CCD image pickup element having about 270,000 picture elements at a horizontal scanning frequency of 9 MHz, and the video signals are converted to digital signals for signal processing in a video signal processor, paired pixel signals from which are combined with a false pixel signal derived from their average. The resulting 3-pixel signals are synchronized with clock pulses at 13.5 MHz to obtain luminance signals and color difference signals conformable to Rec 601, ITU-R standard.
摘要翻译：一种CCD相机，其中通过操作具有水平扫描频率为9MHz的约270,000个图像元素的CCD图像拾取元件获得视频信号，并且将视频信号转换为用于视频信号处理器中的信号处理的数字信号，配对像素信号与从它们的平均值导出的伪像素信号组合。所得到的3像素信号与13.5MHz的时钟脉冲同步，以获得符合ITU-R Rec 601标准的亮度信号和色差信号。

8. 发明申请

WO1999031877A1 MULTI-PROJECTION IMAGE DISPLAY DEVICE 审中-公开
标题翻译：多投影图像显示装置
公开(公告)号：WO1999031877A1
公开(公告)日：1999-06-24
申请号：PCT/JP1997004588
申请日：1997-12-12
申请人： HITACHI, LTD. , YAMASAKI, Masami , TAKEDA, Haruo
发明人： HITACHI, LTD.
IPC分类号： H04N05/74
CPC分类号： H04N9/3147 , H04N9/12
摘要： A multi-projection image display device using a plurality of image projectors to form one picture on a screen, in which images projected from the projectors are smoothly connected with one another, so that seams of the images do not appear conspicuously. The image display device has projectors (0121, 0122, 0123, 0124) and a screen (0140) laid out in such a manner that maximum image projection ranges (0151, 0152, 0153, 0154) of the respective projectors ovelap the adjacent ranges. An image signal control unit (0110) for processing an image signal supplied from an external image input (0180) has, therein, a member for cutting out a partial image area dealt with by each projector, an image converting member for performing geometric transformation and local color correction of the partial image, and an arithmetic control member for controlling the image converting member on the basis of image information inputted from a screen state monitor camera (0130). With this structure, smoothing of the seams between the images may be realized simply by image signal processing, and precise adjustment of the optical system of the projectors becomes unnecessary.
摘要翻译：一种多投影图像显示装置，其使用多个图像投影仪在屏幕上形成一个图像，其中从投影仪投影的图像彼此平滑地连接，使得图像的接缝不显着。图像显示装置具有投影仪（0121，0122，0123，0124）和以相应投影仪的最大图像投影范围（0151,022,033,0154）相邻范围的方式布置的屏幕（0140）。一种用于处理从外部图像输入（0180）提供的图像信号的图像信号控制单元（0110），其中具有用于切割由每个投影仪处理的部分图像区域的部件，用于执行几何变换的图像转换部件，部分图像的局部颜色校正，以及用于基于从屏幕状态监视摄像机（0130）输入的图像信息来控制图像转换部件的运算控制部件。利用这种结构，可以简单地通过图像信号处理来实现图像之间的接缝的平滑化，并且不需要投影仪的光学系统的精确调整。

9. 发明申请

WO1999031656A1 MAGNETIC RECORDING MEDIUM AND MAGNETIC STORAGE 审中-公开
标题翻译：磁记录介质和磁存储
公开(公告)号：WO1999031656A1
公开(公告)日：1999-06-24
申请号：PCT/JP1997004586
申请日：1997-12-12
申请人： HITACHI, LTD. , DAVID, Djulianto Djayaprawira , ISHIKAWA, Akira , KOJIMA, Shuuichi , MATSUDA, Yoshibumi , YAHISA, Yotsuo , SUZUKI, Hiroyuki
发明人： HITACHI, LTD.
IPC分类号： G11B05/66
CPC分类号： G11B5/012
摘要： The ratio BrOR of the residual magnetic flux density in a circumferential direction to the residual magnetic flux density in a radial direction is 0.95 - 1.05 and the ratio HcOR of the coercive force in a circumferential direction to the coercive force in a radial direction is 1.05 - 1.2 in the substrate surface of a magnetic recording medium. Therefore, a high output resolution, a low medium noise and a high track recording density are simultaneously achieved in recording at a high line recording density. When a magnetic storage apparatus is constituted by using a high S/N magnetic recording medium like this, a magnetic disc apparatus which has a high surface recording density, is low in cost and small in size, and a large capacity and a high reliability can be provided.
摘要翻译：圆周方向的剩余磁通密度与径向残留磁通密度的比率BrOR为0.95〜1.05，圆周方向的矫顽力的比率HcOR与径向的矫顽力的比值为1.05〜 1.2在磁记录介质的基板表面中。因此，在高线路记录密度的记录中同时实现高输出分辨率，低中等噪声和高记录密度。当通过使用这样的高S / N磁记录介质构成磁存储装置时，具有高表面记录密度的磁盘装置成本低，尺寸小，容量大，可靠性高提供。

10. 发明申请

WO1999031608A1 METHOD FOR DEVELOPING SYSTEM BOARD 审中-公开
标题翻译：开发系统板的方法
公开(公告)号：WO1999031608A1
公开(公告)日：1999-06-24
申请号：PCT/JP1997004620
申请日：1997-12-16
申请人： HITACHI, LTD. , SHIMIZU, Isao , SATOU, Masayuki
发明人： HITACHI, LTD.
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for developing a system board using a semiconductor integrated circuit device, wherein the development of a system board is made before the development of the circuit device used for the system board is actually acquired by verifying (S31 and S32) whether or not the system board meets the target specifications of the system board by carrying out simulation using a device model in which the functions of the circuit device are modeled by using a function describing language in such a way that the target specifications of the circuit device can be met and the description of the state of the external interface of the circuit device defined conformable to the target specifications. Since the device model in which the functions of the circuit device are described meets the target specifications of the circuit device, the device model is simulated together with the description of the interface state, whether or not the circuit part related to the description of the state of the interface, namely, the interface with the circuit device is appropriate can be verified from the results of the simulation, and the design of the system board can be carried out before the completion of the development of the circuit device or the device is acquired.
摘要翻译：一种用于使用半导体集成电路器件开发系统板的方法，其中系统板的开发是在通过验证（S31和S32）是否实际获取用于系统板的电路器件的开发之前进行的（S31和S32）通过使用使用功能描述语言来对电路装置的功能进行建模的装置模型进行仿真来实现系统板的目标规格，使得可以满足电路装置的目标规格和描述符合目标规格的电路设备外部接口的状态。由于描述了电路装置的功能的装置模型符合电路装置的目标规格，因此将与接口状态的描述一起模拟装置模型，无论电路部分是否与状态描述相关的接口，即与电路设备的接口是合适的，可以从仿真结果中验证，并且系统板的设计可以在完成电路设备或设备的开发之前进行。

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