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1. 发明申请

WO2008033332A3 DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE WITH IMPROVED SCALEABILITY 审中-公开
标题翻译：具有改进的可扩展性的大金属金属绝缘体金属（MIM）器件
公开(公告)号：WO2008033332A3
公开(公告)日：2008-09-18
申请号：PCT/US2007019710
申请日：2007-09-10
申请人： ADVANCED MICRO DEVICES INC , SPANSION LLC , PANGRLE SUZETTE K , AVANZINO STEVEN , HADDAD SAMEER , VANBUSKIRK MICHAEL , RATHOR MANUJ , XIE JAMES , SONG KEVIN , MARRIAN CHRISTIE , CHOO BRYAN , WANG FEI , SHIELDS JEFFREY A
发明人： PANGRLE SUZETTE K , AVANZINO STEVEN , HADDAD SAMEER , VANBUSKIRK MICHAEL , RATHOR MANUJ , XIE JAMES , SONG KEVIN , MARRIAN CHRISTIE , CHOO BRYAN , WANG FEI , SHIELDS JEFFREY A
IPC分类号： H01L45/00 , G11C16/02 , H01L27/24
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer (110), providing an opening (1 12) in the dielectric layer (110), providing a first conductive body ( 116A) in the opening (112), providing a switching body ( 118A) in the opening (112), the first conductive body ( 116A) and switching body (118A) filling the opening (112), and providing a second conductive body (120A) over the switching body (118A). In an alternate embodiment, a second dielectric layer (150) is provided over the first-mentioned dielectric layer (110), and the switching body (156A) is provided in an opening (152) in the second dielectric layer (150).
摘要翻译：制造存储器件的现有方法包括提供电介质层（110）的步骤，在电介质层（110）中提供开口（112），在开口（112）中提供第一导电体（116A），在所述开口（112）中设置切换主体（118A），所述第一导电体（116A）和切换主体（118A）填充所述开口（112），并且在所述开关体（118A）之上提供第二导电体（120A）。在替代实施例中，在第一介电层（110）上提供第二介电层（150），并且开关体（156A）设置在第二介电层（150）的开口（152）中。

2. 发明申请

WO2007064334A1 POLYMER-BASED TRANSISTOR DEVICES, METHODS, AND SYSTEMS 审中-公开
标题翻译：基于聚合物的晶体管器件，方法和系统
公开(公告)号：WO2007064334A1
公开(公告)日：2007-06-07
申请号：PCT/US2005/043788
申请日：2005-12-02
申请人： ADVANCED MICRO DEVICES, INC. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
发明人： BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
IPC分类号： H01L51/05 , H01L29/786
CPC分类号： H01L51/0512 , H01L51/0508
摘要： Disclosed is a semiconductor transistor device (100) with an annular gate (118) surrounding, at least in part, a channel (110) that conducts current between a first (104) and second (114) source/drain. Also disclosed is a semiconductor transistor device (100) having an annular gate (118) and containing a channel (110) composed of a polymer material. Yet also disclosed is the fabrication of a device utilizing a polymer channel (110) surrounded, at least in part, by an annular gate (118). Further disclosed is a system with a means to control (and/or amplify) current via an annular gate (118) surrounding a channel (110) which conducts current between a first (104) and second (114) source/drain.
摘要翻译：公开了具有环形栅极（118）的半导体晶体管器件（100），该环形栅极至少部分地围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）。还公开了具有环形栅极（118）并且包含由聚合物材料构成的沟道（110）的半导体晶体管器件（100）。还公开了使用至少部分由环形栅极（118）包围的聚合物通道（110）的装置的制造。还公开了一种具有通过围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）的环形栅极（118）来控制（和/或扩大）电流的装置的系统。

3. 发明申请

WO2006029280A1 VERTICAL JFET AS USED FOR SELECTIVE COMPONENT IN A MEMORY ARRAY 审中-公开
标题翻译：用于存储阵列中选择性组件的垂直JFET
公开(公告)号：WO2006029280A1
公开(公告)日：2006-03-16
申请号：PCT/US2005/032027
申请日：2005-09-07
申请人： SPANSION LLC , BILL, Colin, S. , VANBUSKIRK, Michael, A.
发明人： BILL, Colin, S. , VANBUSKIRK, Michael, A.
IPC分类号： H01L27/10 , H01L27/098
CPC分类号： H01L27/10 , H01L27/098
摘要： Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell (602) in a memory array while increasing device density in the memory cell array. A vertical JFET (400, 500, 604, 700, 800, 900) is described to which voltages can be selectively applied to control internal current flow there through, which in turn can be employed to manipulate the state of a polymer memory cell (602) coupled to the vertical JFET (400, 500, 604, 700, 800, 900). By mitigating gaps between gates (402, 504, 606, 704, 804, 906), or wordlines (606, 906), and drains (404, 506, 706, 806) of the vertical JFETs (400, 500, 604, 700, 800, 900), feature size can be reduced to permit increased device density. Furthermore, vertical JFETs (400, 500, 604, 700, 800, 900) in the array can be coupled to gates (402, 504, 606, 704, 804, 906) on only two opposite sides, permitting the JFETs (400, 500, 604, 700, 800, 900) to be arranged without gate crossbars between them, further increasing device density. In this manner, the present invention provides switching characteristics to a memory cell and overcomes problematic bulkiness associated with conventional MOS devices.
摘要翻译：公开了系统和方法，其有助于提供存储器阵列中的聚合物存储器单元（602）的选择性功能，同时增加存储器单元阵列中的器件密度。描述了可以选择性地施加电压以控制其中的内部电流的垂直JFET（400,500,600,700,800,900），其可以用于操纵聚合物存储器单元（602 ）耦合到垂直JFET（400,500,600,700,800,900）。通过减轻垂直JFET（400,500,604,700）的门（402,504,606,704,806）或字线（606,906）和漏极（404,506,706,806）之间的间隙，800,900），可以减小特征尺寸以允许增加装置密度。此外，阵列中的垂直JFET（400,500,604,700,800,900）可以仅在两个相对侧耦合到栅极（402,504,606,704,804,906），从而允许JFET（400， 500,604,700,800,900），以便在它们之间没有栅极交叉杆，从而进一步增加了器件密度。以这种方式，本发明向存储器单元提供开关特性，并且克服了与常规MOS器件相关的有问题的体积性。

4. 发明申请

WO2007035284A3 HIGH PERFORMANCE FLASH MEMORY DEVICE USING A PROGRAMMING WINDOW FOR PREDETERMINATION OF BITS TO BE PROGRAMMED AND DC-TO-DC CONVERTER 审中-公开
标题翻译：高性能闪存存储器件使用编程窗口进行编程的器件和直流到直流转换器
公开(公告)号：WO2007035284A3
公开(公告)日：2007-05-31
申请号：PCT/US2006035029
申请日：2006-09-08
申请人： SPANSION LLC , KUO TIAO-HUA , LEONG NANCY , YANG NIAN , WANG GUOWEI , LEE AARON , CHANDRA SACHIT , VANBUSKIRK MICHAEL A , CHEN JOHNNY , HAMILTON DARLENE , LE BINH QUANG
发明人： KUO TIAO-HUA , LEONG NANCY , YANG NIAN , WANG GUOWEI , LEE AARON , CHANDRA SACHIT , VANBUSKIRK MICHAEL A , CHEN JOHNNY , HAMILTON DARLENE , LE BINH QUANG
IPC分类号： G11C16/12 , G11C5/14
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array (102) of memory cells (201), where each memory cell (201) including a substrate (310), a control gate (328), a charge storage element (322), a source region (203) and a drain region (202). The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array (700) and determining which of the predetermined number of bits are to be programmed in the memory array (703). The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array (705). A programming state of the predetermined number of bits in the array is simultaneously verified (708).
摘要翻译：提供了一种用于对包括存储单元阵列（102）的非易失性存储器阵列进行编程的方法，其中每个存储单元（201）包括衬底（310），控制栅极（328），电荷存储元件（322）），源极区（203）和漏极区（202）。该方法包括接收包含要在阵列（700）中编程的预定数量的位的编程窗口，并确定在存储器阵列（703）中哪一个预定位数被编程。预定数量的位同时被编程到阵列中的相应存储单元（705）。同时验证阵列中预定位数的编程状态（708）。

5. 发明申请

WO2006104858A1 WRITE-ONCE READ-MANY TIMES MEMORY 审中-公开
标题翻译：一次写入多个时间记忆
公开(公告)号：WO2006104858A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/010651
申请日：2006-03-24
申请人： SPANSION LLC , VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
发明人： VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device (130) is made up of first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138), and an active layer (136) between the first and second electrodes. The memory device (130) is programmed by providing a charged species from the passive layer (134) into the active layer (136). The memory device (130) may be programmed to have for the programmed memory device (130) a first erase activation energy. The present method provides for the programmed memory device (130) a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入许多次的存储器件（130）由第一和第二电极（132,138），第一和第二电极（132,138）之间的无源层（134）和有源层（ 136）在第一和第二电极之间。存储器件（130）通过将带电物质从无源层（134）提供到有源层（136）来编程。可以将存储器件（130）编程为使编程的存储器件（130）具有第一擦除激活能量。本方法为编程存储器件（130）提供大于第一擦除激活能量的第二擦除激活能量。

6. 发明申请

WO2007035284A2 HIGH PERFORMANCE FLASH MEMORY DEVICE CAPABLE OF HIGH DENSITY DATA STORAGE 审中-公开
标题翻译：具有高密度数据存储能力的高性能闪存存储器件
公开(公告)号：WO2007035284A2
公开(公告)日：2007-03-29
申请号：PCT/US2006/035029
申请日：2006-09-08
申请人： SPANSION LLC , KUO, Tiao-hua , LEONG, Nancy , YANG, Nian , WANG, Guowei , LEE, Aaron , CHANDRA, Sachit , VANBUSKIRK, Michael, A. , CHEN, Johnny , HAMILTON, Darlene , LE, Binh, Quang
发明人： KUO, Tiao-hua , LEONG, Nancy , YANG, Nian , WANG, Guowei , LEE, Aaron , CHANDRA, Sachit , VANBUSKIRK, Michael, A. , CHEN, Johnny , HAMILTON, Darlene , LE, Binh, Quang
IPC分类号： G11C16/12 , G11C5/14
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array (102) of memory cells (201), where each memory cell (201) including a substrate (310), a control gate (328), a charge storage element (322), a source region (203) and a drain region (202). The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array (700) and determining which of the predetermined number of bits are to be programmed in the memory array (703). The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array (705). A programming state of the predetermined number of bits in the array is simultaneously verified (708).
摘要翻译：提供了一种用于对包括存储单元阵列（102）的非易失性存储器阵列进行编程的方法，其中每个存储单元（201）包括衬底（310），控制栅极（328），电荷存储元件（322）），源极区（203）和漏极区（202）。该方法包括接收包含要在阵列（700）中编程的预定数量的位的编程窗口，并确定在存储器阵列（703）中哪一个预定位数被编程。预定数量的位同时被编程到阵列中的相应存储单元（705）。同时验证阵列中预定位数的编程状态（708）。

7. 发明申请

WO2006023338A8 POLYMER MEMORY WITH VARIABLE DATA RETENTION TIME 审中-公开
标题翻译：具有可变数据保留时间的聚合物存储器
公开(公告)号：WO2006023338A8
公开(公告)日：2006-07-27
申请号：PCT/US2005028339
申请日：2005-08-08
申请人： SPANSION LLC , MANDELL AARON , VANBUSKIRK MICHAEL A , SPITZER STUART , KRIEGER JURI H
发明人： MANDELL AARON , VANBUSKIRK MICHAEL A , SPITZER STUART , KRIEGER JURI H
IPC分类号： G11C13/02 , H01L51/05
CPC分类号： G11C13/0016 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/34 , G11C2213/56 , H01L27/285 , H01L51/0595 , H01L2924/0002 , H01L2924/00
摘要： Systems and methodologies are provided for of enabling a polymer memory cell (102, 200) to exhibit variable retention times for stored data therein. Such setting of retention time can depend upon a programming mode and/or type of material employed in the polymer memory cell (102, 200). Short retention times can be obtained by programming the polymer memory cell (102, 200) via a low current or a low electrical field. Similarly, long retention times can be obtained by employing a high current or electrical field to program the polymer memory cell (102, 200).
摘要翻译：提供了系统和方法，用于使聚合物存储器单元（102,200）能够为其中存储的数据展示可变的保留时间。保留时间的这种设置可以取决于在聚合物存储单元（102,200）中使用的编程模式和/或类型的材料。通过经由低电流或低电场对聚合物存储单元（102,200）进行编程，可以获得短的保留时间。类似地，通过使用高电流或电场来编程聚合物存储器单元（102,200）可以获得长的保留时间。

8. 发明申请

WO2006055482A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 审中-公开
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：WO2006055482A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041173
申请日：2005-11-10
申请人： SPANSION LLC , TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
发明人： TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction from the resistive memory cell (130) to the first conductor (BL), and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL), in parallel with the first diode (134), and oriented in the reverse direction from the resistive memory cell (130) to the first conductor (BL). The first and second diodes (134, 132) have different threshold voltages.
摘要翻译：本存储器结构包括第一导体（BL），第二导体（WL），连接到第二导体（WL）的电阻性存储单元（130），连接到电阻式存储单元（130）的第一二极管）和第一导体（BL），并且从正向方向从电阻性存储单元（130）定向到第一导体（BL）;以及第二二极管（132），连接到电阻性存储单元（130）和第一导体（BL），与第一二极管（134）并联，并且从电阻式存储单元（130）到第一导体（BL）的反向定向。第一和第二二极管（134,132）具有不同的阈值电压。

9. 发明申请

WO2006036622A1 CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS 审中-公开
标题翻译：控制可变电阻特性的存储器件
公开(公告)号：WO2006036622A1
公开(公告)日：2006-04-06
申请号：PCT/US2005/033379
申请日：2005-09-19
申请人： ADVANCED MICRO DEVICES, INC. , FANG, Tzu-Ning , VANBUSKIRK, Michael, A. , BILL, Colin, S.
发明人： FANG, Tzu-Ning , VANBUSKIRK, Michael, A. , BILL, Colin, S.
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source (114, 404) to facilitate programming of an organic memory cell (102, 302, 402, 904, 1102, 1206) and/or employing at least one constant voltage source (112, 304) to facilitate erasing of a memory device (200, 300, 400, 900, 1100). The present invention is utilized in single memory cell devices and memory cell arrays (100). Employing a constant current source (114, 404) prevents current spikes during programming and allows accurate control of a memory cell's (102, 302, 402, 904, 1102, 1206) state during write cycles, independent of the cell's resistance. Employing a constant voltage source (112, 304) provides a stable load for memory cells (102, 302, 402, 904, 1102, 1206) during erase cycles and allows for accurate voltage control across the memory cell (102, 302, 402, 904, 1102, 1206) despite large dynamic changes in cell resistance during the process.
摘要翻译：使用至少一个恒流源（114,404）的系统和方法来促进对有机存储器单元（102,302,402,904,1102,1206）的编程

10. 发明申请

WO2008030351A3 MEMORY ERASE USING DISCHARCHING OF CHARGE STORAGE DEVICE 审中-公开
标题翻译：使用电荷储存装置的存储器擦除
公开(公告)号：WO2008030351A3
公开(公告)日：2008-06-19
申请号：PCT/US2007018761
申请日：2007-08-23
申请人： SPANSION LLC , BILL COLIN , MCCLAIN MARK , VANBUSKIRK MICHAEL
发明人： BILL COLIN , MCCLAIN MARK , VANBUSKIRK MICHAEL
IPC分类号： G11C13/00 , G11C16/02
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0076 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A memory erase management system (500) is provided, including providing a resistive change memory cell (102), coupling a first line (118) to the resistive change memory cell (102), coupling a line buffer (140) to the first line (118), providing a charge storage device (144) coupled to the line buffer (140), and performing a single pulse erase of the resistive change memory cell (102) by discharging a current (204) from the charge storage device (144) through the resistive change memory cell (102).
摘要翻译：提供了一种存储器擦除管理系统（500），包括提供电阻变化存储单元（102），将第一行（118）耦合到电阻变化存储单元（102），将行缓冲器（140）耦合到第一行（118），提供耦合到行缓冲器（140）的电荷存储装置（144），以及通过从电荷存储装置（144）放电电流（204）来执行电阻变化存储单元（102）的单次脉冲擦除）通过电阻变化存储单元（102）。

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