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1. 发明申请

WO2006055482A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 审中-公开
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：WO2006055482A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041173
申请日：2005-11-10
申请人： SPANSION LLC , TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
发明人： TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction from the resistive memory cell (130) to the first conductor (BL), and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL), in parallel with the first diode (134), and oriented in the reverse direction from the resistive memory cell (130) to the first conductor (BL). The first and second diodes (134, 132) have different threshold voltages.
摘要翻译：本存储器结构包括第一导体（BL），第二导体（WL），连接到第二导体（WL）的电阻性存储单元（130），连接到电阻式存储单元（130）的第一二极管）和第一导体（BL），并且从正向方向从电阻性存储单元（130）定向到第一导体（BL）;以及第二二极管（132），连接到电阻性存储单元（130）和第一导体（BL），与第一二极管（134）并联，并且从电阻式存储单元（130）到第一导体（BL）的反向定向。第一和第二二极管（134,132）具有不同的阈值电压。

2. 发明申请

WO2005011014A1 MEMORY DEVICE AND METHODS OF USING AND MAKING THE DEVICE 审中-公开
标题翻译：存储器件和使用和制造器件的方法
公开(公告)号：WO2005011014A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/015945
申请日：2004-05-21
申请人： ADVANCED MICRO DEVICES, INC. , LAN, Zhida , VAN BUSKIRK, Michael, A. , BILL, Colin, S.
发明人： LAN, Zhida , VAN BUSKIRK, Michael, A. , BILL, Colin, S.
IPC分类号： H01L51/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/71 , G11C2213/77 , H01L27/24 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0085 , H01L51/0595
摘要： A memory cell (104) made of two electrodes(106, 202, 108, 204) with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media (110) contains an active low conductive layer (112) and passive layer (114). The controllably conductive media (110) changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极（106,202,108,204）制成的存储单元（104）。可控导电介质（110）包含有源低导电层（112）和无源层（114）。当施加电场等外部刺激时，可控导电介质（110）改变其阻抗。还公开了制造存储器件/单元的方法，使用存储器件/单元的方法，以及诸如包含存储器件/单元的计算机的器件。

3. 发明申请

WO2008030351A3 MEMORY ERASE USING DISCHARCHING OF CHARGE STORAGE DEVICE 审中-公开
标题翻译：使用电荷储存装置的存储器擦除
公开(公告)号：WO2008030351A3
公开(公告)日：2008-06-19
申请号：PCT/US2007018761
申请日：2007-08-23
申请人： SPANSION LLC , BILL COLIN , MCCLAIN MARK , VANBUSKIRK MICHAEL
发明人： BILL COLIN , MCCLAIN MARK , VANBUSKIRK MICHAEL
IPC分类号： G11C13/00 , G11C16/02
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0076 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A memory erase management system (500) is provided, including providing a resistive change memory cell (102), coupling a first line (118) to the resistive change memory cell (102), coupling a line buffer (140) to the first line (118), providing a charge storage device (144) coupled to the line buffer (140), and performing a single pulse erase of the resistive change memory cell (102) by discharging a current (204) from the charge storage device (144) through the resistive change memory cell (102).
摘要翻译：提供了一种存储器擦除管理系统（500），包括提供电阻变化存储单元（102），将第一行（118）耦合到电阻变化存储单元（102），将行缓冲器（140）耦合到第一行（118），提供耦合到行缓冲器（140）的电荷存储装置（144），以及通过从电荷存储装置（144）放电电流（204）来执行电阻变化存储单元（102）的单次脉冲擦除）通过电阻变化存储单元（102）。

4. 发明申请

WO2008030351A2 MEMORY ERASE MANAGEMENT SYSTEM 审中-公开
标题翻译：内存删除管理系统
公开(公告)号：WO2008030351A2
公开(公告)日：2008-03-13
申请号：PCT/US2007/018761
申请日：2007-08-23
申请人： SPANSION LLC , BILL, Colin , MCCLAIN, Mark , VANBUSKIRK, Michael
发明人： BILL, Colin , MCCLAIN, Mark , VANBUSKIRK, Michael
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0076 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： A memory erase management system (500) is provided, including providing a resistive change memory cell (102), coupling a first line (118) to the resistive change memory cell (102), coupling a line buffer (140) to the first line (118), providing a charge storage device (144) coupled to the line buffer (140), and performing a single pulse erase of the resistive change memory cell (102) by discharging a current (204) from the charge storage device (144) through the resistive change memory cell (102).
摘要翻译：提供了一种存储器擦除管理系统（500），包括提供电阻变化存储单元（102），将第一行（118）耦合到电阻变化存储单元（102），将行缓冲器（140）耦合到第一行（118），提供耦合到行缓冲器（140）的电荷存储装置（144），以及通过从电荷存储装置（144）放电电流（204）来执行电阻变化存储单元（102）的单次脉冲擦除）通过电阻变化存储单元（102）。

5. 发明申请

WO2007015864A2 PROGRAM/ERASE WAVESHAPING CONTROL TO INCREASE DATA RETENTION OF A MEMORY CELL 审中-公开
标题翻译：程序/擦除波形控制以增加记忆体的数据保留
公开(公告)号：WO2007015864A2
公开(公告)日：2007-02-08
申请号：PCT/US2006027853
申请日：2006-07-17
申请人： SPANSION LLC , FANG TZU-NING , BILL COLIN S , CAI WEI DAISY , GAUN DAVID , GERSHON EUGENE
发明人： FANG TZU-NING , BILL COLIN S , CAI WEI DAISY , GAUN DAVID , GERSHON EUGENE
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0007 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.
摘要翻译：公开了改进和控制存储单元数据保持的系统和方法。产生特定的脉冲宽度和幅度并将其施加到由至少两个电极制成的存储器单元，该至少两个电极在至少两个电极之间具有可控导电的介质。检测存储器单元中的电流，并将较低的输入脉冲发送到存储单元。下部脉冲的应用控制存储器单元的数据保持，而不会干扰存储单元的最终编程状态。

6. 发明申请

WO2006071683A1 METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY 审中-公开
标题翻译：存储二极管阵列中编程，读取和擦除存储器二极管的方法
公开(公告)号：WO2006071683A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/046406
申请日：2005-12-20
申请人： SPANSION LLC , BILL, Colin, S. , KAZA, Swaroop , FANG, Tzu-Ning , SPITZER, Stuart
发明人： BILL, Colin, S. , KAZA, Swaroop , FANG, Tzu-Ning , SPITZER, Stuart
IPC分类号： G11C16/10
CPC分类号： G11C11/36
摘要： A memory array (140) includes first and second sets of conductors (142), (144) and a plurality of memory-diodes (130), each connecting in a forward direction a conductor (BL) of the first set (142) with a conductor (WL) of the second set (144). An electrical potential is applied across a selected memory-diode (130), from higher to lower potential in the forward direction, intended to program the selected memory-diode (130). During this intended programming, each other memory-diode (130) in the array (140) has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode (130) can be established by applying an electrical potential across that memory-diode (130) from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array (140), problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列（140）包括第一和第二组导体（142），（144）和多个存储器二极管（130），每个存储器二极管（130）在前向方向上与第一组（142）的导体（BL）第二组（144）的导体（WL）。在所选择的存储器二极管（130）上施加电势，从正向上的较高电位到较低的电位，用于对所选择的存储器二极管（130）进行编程。在该期望的编程期间，阵列（140）中的每个其它存储器二极管（130）在其正向方向上提供了低于其阈值电压的电位。每个存储二极管（130）的阈值电压可以通过在该存储二极管（130）上施加从相反方向的较高电位到较低电位的电位来建立。通过这样建立足够的阈值电压，并且通过选择施加到阵列（140）的导体的适当电势，避免了与电流泄漏和干扰有关的问题。

7. 发明申请

WO2004102579A1 ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHODS OF OPERATING AND FABRICATING 审中-公开
标题翻译：擦除和编程有机存储器件及其操作和制作方法
公开(公告)号：WO2004102579A1
公开(公告)日：2004-11-25
申请号：PCT/US2004/011811
申请日：2004-04-16
申请人： ADVANCED MICRO DEVICES, INC. , LAN, Zhida , BILL, Colin, S. , VANBUSKIRK, Michael, A.
发明人： LAN, Zhida , BILL, Colin, S. , VANBUSKIRK, Michael, A.
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0009 , G11C13/0016 , G11C2213/15 , G11C2213/56 , G11C2213/71
摘要： An organic memory cell (100, 1300, 1500) made of two electrodes (104, 110, 1304, 1306, 1502, 1504) with a selectively conductive media (106/108, 1308) between the two electrodes (104, 110, 1304, 1306, 1502, 1504) is disclosed. The selectively conductive media (106/108, 1308) contains an organic layer (108, 300, 400, 500) and passive layer (106, 200). The selectively conductive media (106/108, 1308) is programmed by applying bias voltages that program a desired impedance state (1301, 1302, 1303) for a memory cell (100, 1300, 1500). The desired impedance state (1301, 1302, 1303) represents one or more bits of information and the memory cell (100, 1300, 1500) does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media (106/108, 1308) is read by applying a current and reading the impedance of the media (106/108, 1308) in order to determine the impedance state (1301, 1302, 1303) of the memory cell (100, 1300, 1500). Methods of making the organic memory devices/cells (100, 1300, 1500), methods of using the organic memory devices/cells (100, 1300, 1500), and devices such as computers containing the organic memory devices/cells (100, 1300, 1500) are also disclosed.
摘要翻译：由两个电极（104,110,1304,1306,1502,1504）制成的有机存储单元（100,1300,1500）在两个电极（104,110,1304）之间具有选择性导电介质（106/108,1308），1306,1502,1504）。选择性导电介质（106/108,1308）包含有机层（108,300,400,500）和无源层（106,200）。选择性导电介质（106/108,1308）通过施加用于存储单元（100,1300,1500）编程期望的阻抗状态（1301,1301,1303）的偏压来编程。期望的阻抗状态（1301,1301,1303）表示一个或多个信息位，并且存储单元（100,1300,1500）不需要恒定的功率或刷新周期来保持所需的阻抗状态。此外，通过施加电流并读取介质（106/108,1308）的阻抗来读取选择性导电介质（106/108,1308），以便确定存储器的阻抗状态（1301,1301,1303）细胞（100,1300,1500）。制造有机存储器件/单元（100,1300,1500）的方法，使用有机存储器件/单元（100,1300,1500）的方法以及诸如包含有机存储器件/单元（100,1300）的计算机，1500）也被公开。

8. 发明申请

WO2007015864A3 PROGRAM/ERASE WAVESHAPING CONTROL TO INCREASE DATA RETENTION OF A MEMORY CELL 审中-公开
公开(公告)号：WO2007015864A3
公开(公告)日：2007-02-08
申请号：PCT/US2006/027853
申请日：2006-07-17
申请人： SPANSION LLC , FANG, Tzu-ning , BILL, Colin, S. , CAI, Wei, Daisy , GAUN, David , GERSHON, Eugene
发明人： FANG, Tzu-ning , BILL, Colin, S. , CAI, Wei, Daisy , GAUN, David , GERSHON, Eugene
IPC分类号： G11C13/02
摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.

9. 发明申请

WO2006104858A1 WRITE-ONCE READ-MANY TIMES MEMORY 审中-公开
标题翻译：一次写入多个时间记忆
公开(公告)号：WO2006104858A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/010651
申请日：2006-03-24
申请人： SPANSION LLC , VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
发明人： VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device (130) is made up of first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138), and an active layer (136) between the first and second electrodes. The memory device (130) is programmed by providing a charged species from the passive layer (134) into the active layer (136). The memory device (130) may be programmed to have for the programmed memory device (130) a first erase activation energy. The present method provides for the programmed memory device (130) a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入许多次的存储器件（130）由第一和第二电极（132,138），第一和第二电极（132,138）之间的无源层（134）和有源层（ 136）在第一和第二电极之间。存储器件（130）通过将带电物质从无源层（134）提供到有源层（136）来编程。可以将存储器件（130）编程为使编程的存储器件（130）具有第一擦除激活能量。本方法为编程存储器件（130）提供大于第一擦除激活能量的第二擦除激活能量。

10. 发明申请

WO2006102391A3 TEMPERATURE COMPENSATION OF THIN FILM DIODE VOLTAGE THRESHOLD IN MEMORY SENSING CIRCUIT 审中-公开
公开(公告)号：WO2006102391A3
公开(公告)日：2006-09-28
申请号：PCT/US2006/010364
申请日：2006-03-22
申请人： SPANSION LLC , BILL, Colin, S. , CAI, Wei, Daisy
发明人： BILL, Colin, S. , CAI, Wei, Daisy
IPC分类号： G11C7/04 , G11C13/02
摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit (408) and an array core (500) with a temperature variable select device (430). The array core (500) can consist of a thin film diode (430) in series with a nanoscale resistive memory cell (440). The temperature sensitive bias circuit (600) can include a thin film diode (630) in series with two resistors (610, 620) and provides a temperature compensating bias voltage (640) to the array core. The thin film diode (630) of the temperature sensitive bias circuit (600) tracks the diode (430) of the array core (500), while the two resistors (610, 620) create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core (500). The compensating bias reference voltage (640) is generated by the temperature sensitive bias circuit (600), duplicated by a differential amplifier (450), and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell (440).

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