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1. 发明申请

WO2007044226A1 DECODER FOR MEMORY DEVICE WITH LOADING CAPACITOR 审中-公开
标题翻译：具有负载电容器的存储器件解码器
公开(公告)号：WO2007044226A1
公开(公告)日：2007-04-19
申请号：PCT/US2006/037517
申请日：2006-09-26
申请人： SPANSION LLC , YANG, Nian , LAI, Fan, Wan , CHEN, Hounien
发明人： YANG, Nian , LAI, Fan, Wan , CHEN, Hounien
IPC分类号： G11C8/08 , G11C16/08
CPC分类号： G11C8/08 , G11C16/0416 , G11C16/08
摘要： A decoder system for a memory device includes a high voltage pump (204) ' , a high voltage switch (206) , and a loading capacitor (208) . The high voltage pump generates a boost voltage, and the high voltage switch couples one of the boost voltage or a low voltage to a line (VWL) of the memory device. The loading capacitor is coupled to a node (208) between the high voltage pump and the high voltage switch to minimize voltage dipping of the boost volt
摘要翻译：用于存储器件的解码器系统包括高压泵（204），高压开关（206）和负载电容器（208）。高压泵产生升压电压，高压开关将升压或低电压中的一个耦合到存储器件的线（VWL）。负载电容器耦合到高压泵和高电压开关之间的节点（208），以最小化升压电压的电压骤降

2. 发明申请

WO2007021808A1 METHOD OF FORMING GATE ELECTRODE STRUCTURES 审中-公开
标题翻译：形成门电极结构的方法
公开(公告)号：WO2007021808A1
公开(公告)日：2007-02-22
申请号：PCT/US2006/031156
申请日：2006-08-10
申请人： SPANSION LLC , WANG, Zhigang , YANG, Nian , FANG, Shenqing
发明人： WANG, Zhigang , YANG, Nian , FANG, Shenqing
IPC分类号： H01L21/3213
CPC分类号： H01L21/32139 , H01L21/28123
摘要： In one example, the method includes forming a patterned hard mask feature (20A) above a layer of gate electrode material (14), the hard mask feature (20A) having a photoresist feature (16) formed thereabove and the hard mask feature (20A) having a critical dimension (21). The method further includes performing an etching process on the patterned hard mask feature (20A) to produce a reduced hard mask feature (20B) having a critical dimension (21A) that is less than the critical dimension (21) of the patterned hard mask feature (20A) and performing an anisotropic etching process on the layer of gate electrode material (14) using the reduced hard mask feature (20B) as a mask to define a gate electrode (14B).
摘要翻译：在一个示例中，该方法包括在栅极材料层（14）的上方形成图案化的硬掩模特征（20A），硬掩模特征（20A）具有形成在其上的光致抗蚀剂特征（16）和硬掩模特征（20A ）具有临界尺寸（21）。该方法还包括对图案化的硬掩模特征（20A）进行蚀刻处理以产生具有小于图案化硬掩模特征（211）的临界尺寸（21）的临界尺寸（21A）的减小的硬掩模特征（20B）（20A），并且使用所述还原硬掩模特征（20B）作为掩模对所述栅电极材料层（14）进行各向异性蚀刻处理以限定栅电极（14B）。

3. 发明申请

WO2005071749A1 EFFICIENT USE OF WAFER AREA WITH DEVICE UNDER THE PAD APPROACH 审中-公开
标题翻译：有效地利用了基于方法的装置
公开(公告)号：WO2005071749A1
公开(公告)日：2005-08-04
申请号：PCT/US2004/042879
申请日：2004-12-17
申请人： SPANSION, LLC , YANG, Nian , OGAWA, Hiroyuki , WU, Yider , CHANG, Kuo-Tung , SUN, Yu , HAMILTON, Darlene, G.
发明人： YANG, Nian , OGAWA, Hiroyuki , WU, Yider , CHANG, Kuo-Tung , SUN, Yu , HAMILTON, Darlene, G.
IPC分类号： H01L23/485
CPC分类号： H01L27/0203 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： More efficient use of silicon area is achieved by incorporating an active device (25) beneath a pad area (21) of a semiconductor structure (20). The pad area (21) includes a substrate (22) having a first metal layer (23) above it. A second metal layer (26) is below the first metal layer (23). The active device (25) resides in the substrate (22) below the second metal layer (26). A layet of dielectric layer (24) separates the first (26) and second metal layers (23). A via (27) within the dielectric layer (24) electrically couples the first (23) and second metal layers (26). A via (27) connects to the active component (25). Subsequent metal layers (424, 425, 426) can be arranged between the first (23) and second metal layers (26).
摘要翻译：通过在半导体结构（20）的焊盘区域（21）的下方并入有源器件（25）来实现硅面积的更有效的使用。焊盘区域（21）包括在其上方具有第一金属层（23）的基板（22）。第二金属层（26）位于第一金属层（23）的下方。有源器件（25）位于第二金属层（26）下面的衬底（22）中。电介质层（24）的层叠体分离第一（26）和第二金属层（23）。电介质层（24）内的通孔（27）电耦合第一（23）和第二金属层（26）。通孔（27）连接到有源部件（25）。随后的金属层（424,425,426）可以布置在第一（23）和第二金属层（26）之间。

4. 发明申请

WO2007035284A2 HIGH PERFORMANCE FLASH MEMORY DEVICE CAPABLE OF HIGH DENSITY DATA STORAGE 审中-公开
标题翻译：具有高密度数据存储能力的高性能闪存存储器件
公开(公告)号：WO2007035284A2
公开(公告)日：2007-03-29
申请号：PCT/US2006/035029
申请日：2006-09-08
申请人： SPANSION LLC , KUO, Tiao-hua , LEONG, Nancy , YANG, Nian , WANG, Guowei , LEE, Aaron , CHANDRA, Sachit , VANBUSKIRK, Michael, A. , CHEN, Johnny , HAMILTON, Darlene , LE, Binh, Quang
发明人： KUO, Tiao-hua , LEONG, Nancy , YANG, Nian , WANG, Guowei , LEE, Aaron , CHANDRA, Sachit , VANBUSKIRK, Michael, A. , CHEN, Johnny , HAMILTON, Darlene , LE, Binh, Quang
IPC分类号： G11C16/12 , G11C5/14
CPC分类号： G11C5/147 , G11C16/12
摘要： A method is provided for programming a nonvolatile memory array including an array (102) of memory cells (201), where each memory cell (201) including a substrate (310), a control gate (328), a charge storage element (322), a source region (203) and a drain region (202). The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array (700) and determining which of the predetermined number of bits are to be programmed in the memory array (703). The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array (705). A programming state of the predetermined number of bits in the array is simultaneously verified (708).
摘要翻译：提供了一种用于对包括存储单元阵列（102）的非易失性存储器阵列进行编程的方法，其中每个存储单元（201）包括衬底（310），控制栅极（328），电荷存储元件（322）），源极区（203）和漏极区（202）。该方法包括接收包含要在阵列（700）中编程的预定数量的位的编程窗口，并确定在存储器阵列（703）中哪一个预定位数被编程。预定数量的位同时被编程到阵列中的相应存储单元（705）。同时验证阵列中预定位数的编程状态（708）。

5. 发明申请

WO2009002619A1 COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES 审中-公开
标题翻译：用于实现闪存存储器件的均匀编程速度的补偿方法
公开(公告)号：WO2009002619A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/063188
申请日：2008-05-09
申请人： SPANSION LLC , YANG, Nian , LAI, Fan Wan , LEE, Aaron
发明人： YANG, Nian , LAI, Fan Wan , LEE, Aaron
IPC分类号： G06F12/00
CPC分类号： G11C16/30 , G11C16/10
摘要： Systems and methodologies are provided for increasing operation speed uniformity in a flash memory device Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases This difference in distributed substrate resistance can vary voltages supplied to different memory cells In the memory array depending on their location, which can in turn cause non-uniformity In the speed of high voltage operations on the memory array such as programming The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell
摘要翻译：提供了用于提高闪速存储器件中的操作速度均匀性的系统和方法由于典型的闪速存储器阵列的特性，存储器阵列中的存储器单元可能经历分布式衬底电阻，其随着存储器单元的距离从存储器阵列增加这种分布式衬底电阻的差异可以改变提供给不同存储单元的电压在存储器阵列中取决于它们的位置，这反过来会导致不均匀性在存储器阵列上的高电压操作的速度，例如编程本文提供的系统和方法通过至少部分地基于每个相应的存储器单元的位置向存储器阵列中的存储器单元提供补偿的电压电平来降低操作速度的不均匀性

6. 发明申请

WO2007035278A2 MULTI-BIT FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE 审中-公开
标题翻译：具有改进的程序速率的多位闪存存储器件
公开(公告)号：WO2007035278A2
公开(公告)日：2007-03-29
申请号：PCT/US2006/034998
申请日：2006-09-07
申请人： SPANSION LLC , KUO, Tiao-hua , LEONG, Nancy , CHEN, Hounien , CHANDRA, Sachit , YANG, Nian
发明人： KUO, Tiao-hua , LEONG, Nancy , CHEN, Hounien , CHANDRA, Sachit , YANG, Nian
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/10
摘要： A method is provided for programming a nonvolatile memory array (102) including an array of memory cells (201), where each memory cell (201) includes a substrate (315), a control gate (328), a charge storage element (322) having at least two charge storage areas (432, 433) for storing at least two independent charges, a source region (203) and a drain region (202). The method includes designating at least one memory cell as a high-speed memory cell (802) and pre-conditioning the high-speed memory cells (201) by placing a first of the at least two charge storage areas (432, 433) into a programmed state (804), and subsequently enabling the programming on the second area with much higher rate.
摘要翻译：提供一种用于编程包括存储单元阵列（201）的非易失性存储器阵列（102）的方法，其中每个存储单元（201）包括衬底（315），控制栅极（328），电荷存储元件（322））具有用于存储至少两个独立电荷的至少两个电荷存储区（432,433），源极区（203）和漏极区（202）。该方法包括将至少一个存储器单元指定为高速存储单元（802），并且通过将至少两个电荷存储区域（432,433）中的第一个放置在其中来预处理高速存储单元（201）编程状态（804），并且随后以更高的速率启用第二区域上的编程。

7. 发明申请

WO2006014386A1 METHOD OF IMPROVING ERASE VOLTAGE DISTRIBUTION FOR A FLASH MEMORY ARRAY HAVING DUMMY WORDLINES 审中-公开
标题翻译：改进具有双向WILLINES的闪存阵列的擦除电压分配方法
公开(公告)号：WO2006014386A1
公开(公告)日：2006-02-09
申请号：PCT/US2005/023632
申请日：2005-06-30
申请人： SPANSION LLC , WANG, Zhigang , YANG, Nian , FANG, Shenqing
发明人： WANG, Zhigang , YANG, Nian , FANG, Shenqing
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0491 , H01L27/115
摘要： Techniques for erasing memory devices (30) of a flash memory array (4) having a plurality of operative wordlines (22) and at least one dummy wordline (26) adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines.
摘要翻译：公开了一种用于擦除具有多个操作字线（22）的闪存阵列（4）的存储器件（30）和与操作字线末端相邻的至少一个伪字线（26）的技术。擦除存储器件可以包括将栅极电压施加到字线并将偏置电压施加到伪字线。在一种布置中，在伪字线和操作字线的末端之间建立电连接。

8. 发明申请

WO2006022908A1 FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE 审中-公开
标题翻译：闪存存储器单元和编程闪速存储器件的方法
公开(公告)号：WO2006022908A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/014979
申请日：2005-04-29
申请人： SPANSION LLC , WANG, Zhigang , YANG, Nian , LIU, Zhizheng
发明人： WANG, Zhigang , YANG, Nian , LIU, Zhizheng
IPC分类号： G11C16/12
CPC分类号： G11C16/12
摘要： Disclosed are a flash memory unit (12) and a method of programming a flash memory device (28). The method of programming can include applying respective programming voltages to a control gate (32) and a drain (42) of the memory device. A source bias potential can be applied to a source (38) of the memory device. The application of the source bias potential can be controlled with the selective application of one of the programming voltages to a source bias switching device (44).
摘要翻译：公开了一种闪存单元（12）和一种对闪存设备（28）进行编程的方法。编程的方法可以包括将相应的编程电压施加到存储器件的控制栅极（32）和漏极（42）。源极偏置电位可以应用于存储器件的源极（38）。可以通过选择性地将一个编程电压施加到源极偏置开关器件（44）来控制源偏置电位的施加。

9. 发明申请

WO2007035278A3 MULTI - BIT FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE 审中-公开
标题翻译：具有改进程序速率的多位闪存存储器件
公开(公告)号：WO2007035278A3
公开(公告)日：2008-08-07
申请号：PCT/US2006034998
申请日：2006-09-07
申请人： SPANSION LLC , KUO TIAO-HUA , LEONG NANCY , CHEN HOUNIEN , CHANDRA SACHIT , YANG NIAN
发明人： KUO TIAO-HUA , LEONG NANCY , CHEN HOUNIEN , CHANDRA SACHIT , YANG NIAN
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/10
摘要： A method is provided for programming a nonvolatile memory array (102) including an array of memory cells (201), where each memory cell (201) includes a substrate (315), a control gate (328), a charge storage element (322) having at least two charge storage areas (432, 433) for storing at least two independent charges, a source region (203) and a drain region (202). The method includes designating at least one memory cell as a high-speed memory cell (802) and pre-conditioning the high-speed memory cells (201) by placing a first of the at least two charge storage areas (432, 433) into a programmed state (804), and subsequently enabling the programming on the second area with much higher rate.
摘要翻译：提供一种用于编程包括存储单元阵列（201）的非易失性存储器阵列（102）的方法，其中每个存储单元（201）包括衬底（315），控制栅极（328），电荷存储元件（322））具有用于存储至少两个独立电荷的至少两个电荷存储区（432,433），源极区（203）和漏极区（202）。该方法包括将至少一个存储器单元指定为高速存储单元（802），并且通过将至少两个电荷存储区域（432,433）中的第一个放置在其中来预处理高速存储单元（201）编程状态（804），并且随后以更高的速率启用第二区域上的编程。

10. 发明申请

WO2008076656A1 ERASE METHOD FOR A MEMORY INCLUDING SOFT PROGRAMMING 审中-公开
标题翻译：包含软编程的存储器的擦除方法
公开(公告)号：WO2008076656A1
公开(公告)日：2008-06-26
申请号：PCT/US2007/086647
申请日：2007-12-06
申请人： SPANSION LLC , YANG, Nian , WU, Yonggang , YANG, Tien-chun
发明人： YANG, Nian , WU, Yonggang , YANG, Tien-chun
IPC分类号： G11C16/34
CPC分类号： G11C16/3404 , G11C16/0475
摘要： One embodiment of the invention relates to a method (500) for accessing a memory cell (400). In this method, at least one bit of the memory cell is erased in block (506). After erasing the at least one bit, a soft program operation is performed in block (508) to bias the memory cell thereby improving the reliability of data stored in the memory cell. Other methods and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及一种用于访问存储器单元（400）的方法（500）。在该方法中，块（506）中擦除存储单元的至少一位。在擦除至少一个位之后，在块（508）中执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。还公开了其它方法和系统。

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