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1. 发明申请

WO2012050812A3 SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS 审中-公开
公开(公告)号：WO2012050812A3
公开(公告)日：2012-04-19
申请号：PCT/US2011/053294
申请日：2011-09-26
申请人： VERTICAL CIRCUITS, INC. , BARRIE, Keith, Lake , PANGRLE, Suzette, K. , VILLAVICECIO, Grant , LEAL, Jeffrey, S.
发明人： BARRIE, Keith, Lake , PANGRLE, Suzette, K. , VILLAVICECIO, Grant , LEAL, Jeffrey, S.
IPC分类号： H01L21/60
摘要： A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.

2. 发明申请

WO2004109803A1 PLANAR POLYMER MEMORY DEVICE 审中-公开
标题翻译：平面聚合物存储器件
公开(公告)号：WO2004109803A1
公开(公告)日：2004-12-16
申请号：PCT/US2004/014696
申请日：2004-05-11
申请人： ADVANCED MICRO DEVICES, INC. , TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , OKOROANYANWU, Uzodinma , PANGRLE, Suzette, K.
发明人： TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , OKOROANYANWU, Uzodinma , PANGRLE, Suzette, K.
IPC分类号： H01L27/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0575
摘要： The present invention provides a planar polymer memory device (100) that can operate as a non-volatile memory device. A planar polymer memory device (100) can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device (100) comprises at least one of forming a first electrode (125) with an associated plug, forming a second electrode (140), forming a passive layer (130) over the extension, depositing an organic polymer and patterning the organic polymer (115). The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device (100) to facilitate programming. The TFD can be formed between the first electrode (125) and the selectively conductive medium or the second electrode (140) and the selectively conductive medium.
摘要翻译：本发明提供可作为非易失性存储器件操作的平面聚合物存储器件（100）。平面聚合物存储器件（100）可以形成有两个或更多个电极和与一个电极相关联的电极延伸部分，其中选择性导电介质和电介质分离电极。用于形成平面聚合物存储器件（100）的方法包括形成具有相关插塞的第一电极（125），形成第二电极（140），在延伸部分上形成钝化层（130），沉积有机聚合物和图案化有机聚合物（115）。该方法将平面聚合物存储器件集成到半导体制造工艺中。还可以与平面聚合物存储器件（100）一起使用薄膜二极管（TFD），以便于编程。 TFD可以形成在第一电极（125）和选择性导电介质或第二电极（140）和选择性导电介质之间。

3. 发明申请

WO2011146579A8 ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES 审中-公开
标题翻译：堆叠式模具组件的模垫和Z型互连之间的电连接器
公开(公告)号：WO2011146579A8
公开(公告)日：2012-12-20
申请号：PCT/US2011036941
申请日：2011-05-18
申请人： INVENSAS CORP , CO REYNALDO , LEAL JEFFREY S , PANGRLE SUZETTE K , MCGRATH SCOTT , MELCHER DEANN EILEEN , BARRIE KEITH L , VILLAVICENCIO GRANT , DEL ROSARIO ELMER M , BRAY JOHN R
发明人： CO REYNALDO , LEAL JEFFREY S , PANGRLE SUZETTE K , MCGRATH SCOTT , MELCHER DEANN EILEEN , BARRIE KEITH L , VILLAVICENCIO GRANT , DEL ROSARIO ELMER M , BRAY JOHN R
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/6836 , H01L21/78 , H01L23/3171 , H01L23/3185 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2224/02371 , H01L2224/03002 , H01L2224/03318 , H01L2224/0332 , H01L2224/03632 , H01L2224/03848 , H01L2224/05016 , H01L2224/05017 , H01L2224/0529 , H01L2224/05553 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/94 , H01L2225/06551 , H01L2225/06562 , H01L2225/06568 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2224/03
摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
摘要翻译：用于在晶片级处理中在管芯焊盘上形成连接器的方法包括在管芯焊盘上方形成可固化导电材料的斑点并且延伸至互连芯片边缘或在互连芯片边缘之上延伸; 固化导电材料; 并在此后的晶圆切割过程中切断斑点。而且，管芯焊盘用于z互连由这些方法形成的连接器，并且相应地被成形和确定尺寸。而且，根据所述方法制备的堆叠的管芯组件和堆叠的管芯封装包含管芯，并且具有管芯焊盘以z互连由所述方法形成的连接器，并且相应地成形和确定尺寸。

4. 发明申请

WO2011056987A2 STACKED DIE ASSEMBLY HAVING REDUCED STRESS ELECTRICAL INTERCONNECTS 审中-公开
标题翻译：堆叠的模具组件具有降低的应力电连接
公开(公告)号：WO2011056987A2
公开(公告)日：2011-05-12
申请号：PCT/US2010055472
申请日：2010-11-04
申请人： VERTICAL CIRCUITS INC , MCGRATH SCOTT , LEAL JEFFREY S , SHENOY RAVI , CANTILLEP LORETO , MCELREA SIMON J S , PANGRLE SUZETTE K
发明人： MCGRATH SCOTT , LEAL JEFFREY S , SHENOY RAVI , CANTILLEP LORETO , MCELREA SIMON J S , PANGRLE SUZETTE K
IPC分类号： H01L23/48 , H01L23/12
CPC分类号： H01L21/563 , H01L23/3121 , H01L23/49805 , H01L23/562 , H01L24/06 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/82 , H01L25/0657 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/16225 , H01L2224/24011 , H01L2224/24051 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/73203 , H01L2224/76155 , H01L2224/82102 , H01L2225/06517 , H01L2225/06551 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2924/00
摘要： Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.
摘要翻译：公开了用于改进堆叠的模组件中的电互连的方法，并且公开了具有通过这些方法形成的结构特征的堆叠的模组件。所产生的堆叠模具组件的特征在于具有减少的电连接失效。

5. 发明申请

WO2006053163A3 PROTECTION OF ACTIVE LAYERS OF MEMORY CELLS DURING PROCESSING OF OTHER ELEMENTS 审中-公开
标题翻译：在处理其他元素期间保护活动层的记忆细胞
公开(公告)号：WO2006053163A3
公开(公告)日：2006-08-03
申请号：PCT/US2005040826
申请日：2005-11-10
申请人： SPANSION LLC , AVANZINO STEVEN , SOKOLIK IGOR , PANGRLE SUZETTE K , TRIPSAS NICHOLAS H , SHIELDS JEFFREY A
发明人： AVANZINO STEVEN , SOKOLIK IGOR , PANGRLE SUZETTE K , TRIPSAS NICHOLAS H , SHIELDS JEFFREY A
IPC分类号： H01L45/00
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A method of fabricating an electronic structure by providing a conductive layer (102), providing a dielectric layer (100) over the conductive layer (102), providing first and second openings (104, 106) through the dielectric layer (100), providing first and second conductive bodies (108, 110) in the first and second openings (104, 106) respectively and in contact with the conductive layer (102), providing a memory structure (126) over the first conductive body (108), providing a protective element (134) over the memory structure (126), and undertaking processing on the second conductive body (110).
摘要翻译：一种通过提供导电层（102）制造电子结构的方法，在导电层（102）上提供介电层（100），通过介电层（100）提供第一和第二开口（104,106），提供分别在第一和第二开口（104,106）中并与导电层（102）接触的第一和第二导电体（108,110），在第一导电体（108）上提供存储结构（126），提供在所述存储器结构（126）上方的保护元件（134），并且对所述第二导电体（110）进行处理。

6. 发明申请

WO2006055482A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 审中-公开
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：WO2006055482A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041173
申请日：2005-11-10
申请人： SPANSION LLC , TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
发明人： TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction from the resistive memory cell (130) to the first conductor (BL), and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL), in parallel with the first diode (134), and oriented in the reverse direction from the resistive memory cell (130) to the first conductor (BL). The first and second diodes (134, 132) have different threshold voltages.
摘要翻译：本存储器结构包括第一导体（BL），第二导体（WL），连接到第二导体（WL）的电阻性存储单元（130），连接到电阻式存储单元（130）的第一二极管）和第一导体（BL），并且从正向方向从电阻性存储单元（130）定向到第一导体（BL）;以及第二二极管（132），连接到电阻性存储单元（130）和第一导体（BL），与第一二极管（134）并联，并且从电阻式存储单元（130）到第一导体（BL）的反向定向。第一和第二二极管（134,132）具有不同的阈值电压。

7. 发明申请

WO2011056987A3 STACKED DIE ASSEMBLY HAVING REDUCED STRESS ELECTRICAL INTERCONNECTS 审中-公开
公开(公告)号：WO2011056987A3
公开(公告)日：2011-05-12
申请号：PCT/US2010/055472
申请日：2010-11-04
申请人： VERTICAL CIRCUITS, INC. , McGRATH, Scott , LEAL, Jeffrey, S. , SHENOY, Ravi , CANTILLEP, Loreto , McELREA, Simon, J.S. , PANGRLE, Suzette, K.
发明人： McGRATH, Scott , LEAL, Jeffrey, S. , SHENOY, Ravi , CANTILLEP, Loreto , McELREA, Simon, J.S. , PANGRLE, Suzette, K.
IPC分类号： H01L23/48 , H01L23/12
摘要： Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

8. 发明申请

WO2008033332A2 DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE WITH IMPROVED SCALEABILITY 审中-公开
标题翻译：具有改进的可分级性的金属绝缘体 - 金属（MIM）器件
公开(公告)号：WO2008033332A2
公开(公告)日：2008-03-20
申请号：PCT/US2007/019710
申请日：2007-09-10
申请人： ADVANCED MICRO DEVICES, INC. , SPANSION LLC , PANGRLE, Suzette, K. , AVANZINO, Steven , HADDAD, Sameer , VANBUSKIRK, Michael , RATHOR, Manuj , XIE, James , SONG, Kevin , MARRIAN, Christie , CHOO, Bryan , WANG, Fei , SHIELDS, Jeffrey, A.
发明人： PANGRLE, Suzette, K. , AVANZINO, Steven , HADDAD, Sameer , VANBUSKIRK, Michael , RATHOR, Manuj , XIE, James , SONG, Kevin , MARRIAN, Christie , CHOO, Bryan , WANG, Fei , SHIELDS, Jeffrey, A.
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , H01L45/1683
摘要： A present method of fabricating a memory device includes the steps of providing a dielectric layer (110), providing an opening (1 12) in the dielectric layer (110), providing a first conductive body ( 116A) in the opening (112), providing a switching body ( 118A) in the opening (112), the first conductive body ( 116A) and switching body (118A) filling the opening (112), and providing a second conductive body (120A) over the switching body (118A). In an alternate embodiment, a second dielectric layer (150) is provided over the first-mentioned dielectric layer (110), and the switching body (156A) is provided in an opening (152) in the second dielectric layer (150).
摘要翻译：制造存储器件的当前方法包括以下步骤：提供介电层（110），在介电层（110）中提供开口（112），提供第一导电体（116A ）在开口（112）中，在开口（112）中提供切换主体（118A），第一导电主体（116A）和开关主体（118A）填充开口（112），并且提供第二导电主体（120A ）在切换体（118A）上方。在替代实施例中，在第一介电层（110）上提供第二介电层（150），并且在第二介电层（150）中的开口（152）中提供开关体（156A） / p>

9. 发明申请

WO2007005872A1 RESITIVE MEMORY DEVICE WITH IMPROVED DATA RETENTION 审中-公开
标题翻译：具有改进的数据保留的可重构存储器件
公开(公告)号：WO2007005872A1
公开(公告)日：2007-01-11
申请号：PCT/US2006/026044
申请日：2006-06-30
申请人： SPANSION LLC , SOKOLIK, Igor , KINGSBOROUGH, Richard , GAUN, David , KAZA, Swaroop , SPITZER, Stuart , PANGRLE, Suzette, K.
发明人： SOKOLIK, Igor , KINGSBOROUGH, Richard , GAUN, David , KAZA, Swaroop , SPITZER, Stuart , PANGRLE, Suzette, K.
IPC分类号： G11C13/02 , H01L27/28
CPC分类号： G11C13/0016 , B82Y10/00 , G11C13/0014 , G11C2213/11 , G11C2213/56
摘要： The present memory device (130) includes first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138) and an active layer (136) between the first and second electrodes (132, 138), the active layer (136) being of a material containing randomly oriented pores which are interconnected to form passages through the active layer (136).
摘要翻译：本存储器件（130）包括第一和第二电极（132,138），位于第一和第二电极（132,138）之间的钝化层（134）和第一和第二电极之间的有源层（136），138），所述活性层（136）是含有随机取向的孔的材料，其互连以形成通过所述活性层（136）的通道。

10. 发明申请

WO2005010892A1 POLYMER MEMORY DEVICE FORMED IN VIA OPENING 审中-公开
标题翻译：聚合物存储器件通过开放形成
公开(公告)号：WO2005010892A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/014797
申请日：2004-05-11
申请人： ADVANCED MICRO DEVICES, INC. , TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , PANGRLE, Suzette, K. , OKOROANYANWU, Uzodinma , HUI, Angela, T. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , LOPATIN, Sergey, D. , NGO, Minh, Van , KHATHURIA, Ashok, M. , CHANG, Mark, S. , CHEUNG, Patrick, K. , OGLESBY, Jane, V.
发明人： TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , PANGRLE, Suzette, K. , OKOROANYANWU, Uzodinma , HUI, Angela, T. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , LOPATIN, Sergey, D. , NGO, Minh, Van , KHATHURIA, Ashok, M. , CHANG, Mark, S. , CHEUNG, Patrick, K. , OGLESBY, Jane, V.
IPC分类号： G11C13/02
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

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