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1. 发明申请

WO2007064334A1 POLYMER-BASED TRANSISTOR DEVICES, METHODS, AND SYSTEMS 审中-公开
标题翻译：基于聚合物的晶体管器件，方法和系统
公开(公告)号：WO2007064334A1
公开(公告)日：2007-06-07
申请号：PCT/US2005/043788
申请日：2005-12-02
申请人： ADVANCED MICRO DEVICES, INC. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
发明人： BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
IPC分类号： H01L51/05 , H01L29/786
CPC分类号： H01L51/0512 , H01L51/0508
摘要： Disclosed is a semiconductor transistor device (100) with an annular gate (118) surrounding, at least in part, a channel (110) that conducts current between a first (104) and second (114) source/drain. Also disclosed is a semiconductor transistor device (100) having an annular gate (118) and containing a channel (110) composed of a polymer material. Yet also disclosed is the fabrication of a device utilizing a polymer channel (110) surrounded, at least in part, by an annular gate (118). Further disclosed is a system with a means to control (and/or amplify) current via an annular gate (118) surrounding a channel (110) which conducts current between a first (104) and second (114) source/drain.
摘要翻译：公开了具有环形栅极（118）的半导体晶体管器件（100），该环形栅极至少部分地围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）。还公开了具有环形栅极（118）并且包含由聚合物材料构成的沟道（110）的半导体晶体管器件（100）。还公开了使用至少部分由环形栅极（118）包围的聚合物通道（110）的装置的制造。还公开了一种具有通过围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）的环形栅极（118）来控制（和/或扩大）电流的装置的系统。

2. 发明申请

WO2006104858A1 WRITE-ONCE READ-MANY TIMES MEMORY 审中-公开
标题翻译：一次写入多个时间记忆
公开(公告)号：WO2006104858A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/010651
申请日：2006-03-24
申请人： SPANSION LLC , VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
发明人： VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device (130) is made up of first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138), and an active layer (136) between the first and second electrodes. The memory device (130) is programmed by providing a charged species from the passive layer (134) into the active layer (136). The memory device (130) may be programmed to have for the programmed memory device (130) a first erase activation energy. The present method provides for the programmed memory device (130) a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入许多次的存储器件（130）由第一和第二电极（132,138），第一和第二电极（132,138）之间的无源层（134）和有源层（ 136）在第一和第二电极之间。存储器件（130）通过将带电物质从无源层（134）提供到有源层（136）来编程。可以将存储器件（130）编程为使编程的存储器件（130）具有第一擦除激活能量。本方法为编程存储器件（130）提供大于第一擦除激活能量的第二擦除激活能量。

3. 发明申请

WO2004102579A1 ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHODS OF OPERATING AND FABRICATING 审中-公开
标题翻译：擦除和编程有机存储器件及其操作和制作方法
公开(公告)号：WO2004102579A1
公开(公告)日：2004-11-25
申请号：PCT/US2004/011811
申请日：2004-04-16
申请人： ADVANCED MICRO DEVICES, INC. , LAN, Zhida , BILL, Colin, S. , VANBUSKIRK, Michael, A.
发明人： LAN, Zhida , BILL, Colin, S. , VANBUSKIRK, Michael, A.
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0009 , G11C13/0016 , G11C2213/15 , G11C2213/56 , G11C2213/71
摘要： An organic memory cell (100, 1300, 1500) made of two electrodes (104, 110, 1304, 1306, 1502, 1504) with a selectively conductive media (106/108, 1308) between the two electrodes (104, 110, 1304, 1306, 1502, 1504) is disclosed. The selectively conductive media (106/108, 1308) contains an organic layer (108, 300, 400, 500) and passive layer (106, 200). The selectively conductive media (106/108, 1308) is programmed by applying bias voltages that program a desired impedance state (1301, 1302, 1303) for a memory cell (100, 1300, 1500). The desired impedance state (1301, 1302, 1303) represents one or more bits of information and the memory cell (100, 1300, 1500) does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media (106/108, 1308) is read by applying a current and reading the impedance of the media (106/108, 1308) in order to determine the impedance state (1301, 1302, 1303) of the memory cell (100, 1300, 1500). Methods of making the organic memory devices/cells (100, 1300, 1500), methods of using the organic memory devices/cells (100, 1300, 1500), and devices such as computers containing the organic memory devices/cells (100, 1300, 1500) are also disclosed.
摘要翻译：由两个电极（104,110,1304,1306,1502,1504）制成的有机存储单元（100,1300,1500）在两个电极（104,110,1304）之间具有选择性导电介质（106/108,1308），1306,1502,1504）。选择性导电介质（106/108,1308）包含有机层（108,300,400,500）和无源层（106,200）。选择性导电介质（106/108,1308）通过施加用于存储单元（100,1300,1500）编程期望的阻抗状态（1301,1301,1303）的偏压来编程。期望的阻抗状态（1301,1301,1303）表示一个或多个信息位，并且存储单元（100,1300,1500）不需要恒定的功率或刷新周期来保持所需的阻抗状态。此外，通过施加电流并读取介质（106/108,1308）的阻抗来读取选择性导电介质（106/108,1308），以便确定存储器的阻抗状态（1301,1301,1303）细胞（100,1300,1500）。制造有机存储器件/单元（100,1300,1500）的方法，使用有机存储器件/单元（100,1300,1500）的方法以及诸如包含有机存储器件/单元（100,1300）的计算机，1500）也被公开。

4. 发明申请

WO2005011014A1 MEMORY DEVICE AND METHODS OF USING AND MAKING THE DEVICE 审中-公开
标题翻译：存储器件和使用和制造器件的方法
公开(公告)号：WO2005011014A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/015945
申请日：2004-05-21
申请人： ADVANCED MICRO DEVICES, INC. , LAN, Zhida , VAN BUSKIRK, Michael, A. , BILL, Colin, S.
发明人： LAN, Zhida , VAN BUSKIRK, Michael, A. , BILL, Colin, S.
IPC分类号： H01L51/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/71 , G11C2213/77 , H01L27/24 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0085 , H01L51/0595
摘要： A memory cell (104) made of two electrodes(106, 202, 108, 204) with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media (110) contains an active low conductive layer (112) and passive layer (114). The controllably conductive media (110) changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极（106,202,108,204）制成的存储单元（104）。可控导电介质（110）包含有源低导电层（112）和无源层（114）。当施加电场等外部刺激时，可控导电介质（110）改变其阻抗。还公开了制造存储器件/单元的方法，使用存储器件/单元的方法，以及诸如包含存储器件/单元的计算机的器件。

5. 发明申请

WO2011123465A1 METHOD AND SYSTEM FOR UTILIZING PEROVSKITE MATERIAL FOR CHARGE STORAGE AND AS A DIELECTRIC 审中-公开
标题翻译：用于充电储存和作为电介质的PEROVSKITE材料的方法和系统
公开(公告)号：WO2011123465A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/030382
申请日：2011-03-29
申请人： 4D-S PTY LTD. , LAN, Zhida
发明人： LAN, Zhida
IPC分类号： B32B9/00 , H01L21/02
CPC分类号： G11C11/22 , G11C13/0007 , H01L21/28291 , H01L27/11507 , H01L28/55 , H01L29/51 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： A memory device is disclosed. In a first aspect the memory comprises a first doped awell; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovsite material on top of the first doped well and located between two bitlines; and a wordline located above the Perovskite material. In a second aspect the memory comprises a first doped well; two wells of opposite doping implanted in the first doped well; and two bitlines located on top of the two wells. The memory includes a Perovskite material located within one of the bitlines and a wordline located above the first doped well and located between the two bitlines.
摘要翻译：公开了一种存储器件。在第一方面，存储器包括第一掺杂awell; 在第一掺杂井中注入相反掺杂的两个阱; 位于两口井顶部的两条位线。存储器包括位于第一掺杂阱顶部并位于两个位线之间的细胞壁材料; 和位于钙钛矿材料上方的字线。在第二方面，存储器包括第一掺杂阱; 在第一掺杂井中注入相反掺杂的两个阱; 位于两口井顶部的两条位线。存储器包括位于位线之一内的钙钛矿材料和位于第一掺杂阱之上并位于两个位线之间的字线。

6. 发明申请

WO2006104824A2 MEMORY DEVICE WITH IMPROVED DATA RETENTION 审中-公开
标题翻译：具有改进的数据保留的存储器件
公开(公告)号：WO2006104824A2
公开(公告)日：2006-10-05
申请号：PCT/US2006/010545
申请日：2006-03-24
申请人： SPANSION LLC , LAN, Zhida , HADDAD, Sameer , AVANZINO, Steven
发明人： LAN, Zhida , HADDAD, Sameer , AVANZINO, Steven
IPC分类号： H01L45/00 , G11C13/02
CPC分类号： G11C13/0009 , G11C2213/11 , G11C2213/15 , G11C2213/34 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L2924/0002 , H01L2924/00
摘要： The present memory device (130) include first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138), and an active layer (136) between the first and second electrodes (132, 138) and into which ions from the passive layer (134) may be provided, and from which the ions may be provided into the passive layer (134). The active layer (136) is made up of a base material and an impurity therein. The combined the material and impurity have a lower diffusion coefficient than the base material alone.
摘要翻译：本存储器件（130）包括第一和第二电极（132,138），位于第一和第二电极（132,138）之间的无源层（134）和第一和第二电极之间的有源层（136） 132，138），并且可以提供来自被动层（134）的离子，并且离子可从该离子提供到被动层（134）中。有源层（136）由基材和杂质构成。材料和杂质的组合具有比单独的基材更低的扩散系数。

7. 发明申请

WO2004042738A1 CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES 审中-公开
标题翻译：使用ZENER二极管器件控制存储器阵列
公开(公告)号：WO2004042738A1
公开(公告)日：2004-05-21
申请号：PCT/US2003/021680
申请日：2003-07-10
申请人： ADVANCED MICRO DEVICES, INC.
发明人： VANBUSKIRK, Michael, A. , FANG, Tzu-Ning , BILL, Colin, S. , LAN, Zhida
IPC分类号： G11C16/02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , G11C13/003 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array (100, 200, 212, 300, 400). State change voltages can be applied to a single device in the array (100, 200, 212, 300, 400) of semiconductor devices without the need for transistor-type voltage controls. The diodic effect (114, 508, 510, 900, 1014, 1114, 1214, 1502, 1702, 1812) of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
摘要翻译：本发明通过辅助单个器件改变半导体阵列（100,200,212,300,400）中的状态的方式来有助于半导体器件。可以将状态变化电压施加到半导体器件的阵列（100,200,212,300,400）中的单个器件，而不需要晶体管型电压控制。本发明的二体效应（114,508,510,910,1014,1114,1214,1502,1702,1812）通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进这种活动。以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

8. 发明申请

WO2013101499A2 LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE 审中-公开
标题翻译：低成型电压非易失存储器件
公开(公告)号：WO2013101499A2
公开(公告)日：2013-07-04
申请号：PCT/US2012/069676
申请日：2012-12-14
申请人： SANDISK TECHNOLOGIES, INC. , LAN, Zhida , SCHEUERLEIN, Roy, E. , ZHANG, Tong , HOU, Kun , RATNAM, Perumal
发明人： LAN, Zhida , SCHEUERLEIN, Roy, E. , ZHANG, Tong , HOU, Kun , RATNAM, Perumal
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储元件设置在跨越半导体衬底的不同距离上的多个平面中。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流被限制。在具有极性的成形期间，将形成电压施加到存储元件，使得位线用作阴极，并且字线用作阳极，阴极与开关材料相比具有较低的电子注入能量势垒。

9. 发明申请

WO2013058853A1 NON-VOLATILE MEMORY CELL COMPRISING METAL OXIDE RESISTIVE MEMORY ELEMENT AND AN ANTIFUSE LAYER 审中-公开
标题翻译：包含金属氧化物电阻记忆元件和抗反射层的非易失性存储单元
公开(公告)号：WO2013058853A1
公开(公告)日：2013-04-25
申请号：PCT/US2012/048232
申请日：2012-07-26
申请人： SANDISK 3D LLC , HOU, Kun , CHEN, Yung-Tin , LAN, Zhida , XU, Huiwen
发明人： HOU, Kun , CHEN, Yung-Tin , LAN, Zhida , XU, Huiwen
IPC分类号： G11C17/16 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C17/16 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/51 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A non-volatile memory cell includes a first electrode, a steering element, a metal oxide storage element located in series with the steering element, a dielectric resistor located in series with the steering element and the metal oxide storage element, and a second electrode.
摘要翻译：非易失性存储单元包括与转向元件串联设置的第一电极，操舵元件，金属氧化物存储元件，与转向元件和金属氧化物存储元件串联的介质电阻器和第二电极。

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