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1. 发明申请

WO2006055482A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 审中-公开
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：WO2006055482A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041173
申请日：2005-11-10
申请人： SPANSION LLC , TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
发明人： TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction from the resistive memory cell (130) to the first conductor (BL), and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL), in parallel with the first diode (134), and oriented in the reverse direction from the resistive memory cell (130) to the first conductor (BL). The first and second diodes (134, 132) have different threshold voltages.
摘要翻译：本存储器结构包括第一导体（BL），第二导体（WL），连接到第二导体（WL）的电阻性存储单元（130），连接到电阻式存储单元（130）的第一二极管）和第一导体（BL），并且从正向方向从电阻性存储单元（130）定向到第一导体（BL）;以及第二二极管（132），连接到电阻性存储单元（130）和第一导体（BL），与第一二极管（134）并联，并且从电阻式存储单元（130）到第一导体（BL）的反向定向。第一和第二二极管（134,132）具有不同的阈值电压。

2. 发明申请

WO2007015864A3 PROGRAM/ERASE WAVESHAPING CONTROL TO INCREASE DATA RETENTION OF A MEMORY CELL 审中-公开
公开(公告)号：WO2007015864A3
公开(公告)日：2007-02-08
申请号：PCT/US2006/027853
申请日：2006-07-17
申请人： SPANSION LLC , FANG, Tzu-ning , BILL, Colin, S. , CAI, Wei, Daisy , GAUN, David , GERSHON, Eugene
发明人： FANG, Tzu-ning , BILL, Colin, S. , CAI, Wei, Daisy , GAUN, David , GERSHON, Eugene
IPC分类号： G11C13/02
摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.

3. 发明申请

WO2006104858A1 WRITE-ONCE READ-MANY TIMES MEMORY 审中-公开
标题翻译：一次写入多个时间记忆
公开(公告)号：WO2006104858A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/010651
申请日：2006-03-24
申请人： SPANSION LLC , VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
发明人： VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device (130) is made up of first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138), and an active layer (136) between the first and second electrodes. The memory device (130) is programmed by providing a charged species from the passive layer (134) into the active layer (136). The memory device (130) may be programmed to have for the programmed memory device (130) a first erase activation energy. The present method provides for the programmed memory device (130) a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入许多次的存储器件（130）由第一和第二电极（132,138），第一和第二电极（132,138）之间的无源层（134）和有源层（ 136）在第一和第二电极之间。存储器件（130）通过将带电物质从无源层（134）提供到有源层（136）来编程。可以将存储器件（130）编程为使编程的存储器件（130）具有第一擦除激活能量。本方法为编程存储器件（130）提供大于第一擦除激活能量的第二擦除激活能量。

4. 发明申请

WO2006036622A1 CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS 审中-公开
标题翻译：控制可变电阻特性的存储器件
公开(公告)号：WO2006036622A1
公开(公告)日：2006-04-06
申请号：PCT/US2005/033379
申请日：2005-09-19
申请人： ADVANCED MICRO DEVICES, INC. , FANG, Tzu-Ning , VANBUSKIRK, Michael, A. , BILL, Colin, S.
发明人： FANG, Tzu-Ning , VANBUSKIRK, Michael, A. , BILL, Colin, S.
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source (114, 404) to facilitate programming of an organic memory cell (102, 302, 402, 904, 1102, 1206) and/or employing at least one constant voltage source (112, 304) to facilitate erasing of a memory device (200, 300, 400, 900, 1100). The present invention is utilized in single memory cell devices and memory cell arrays (100). Employing a constant current source (114, 404) prevents current spikes during programming and allows accurate control of a memory cell's (102, 302, 402, 904, 1102, 1206) state during write cycles, independent of the cell's resistance. Employing a constant voltage source (112, 304) provides a stable load for memory cells (102, 302, 402, 904, 1102, 1206) during erase cycles and allows for accurate voltage control across the memory cell (102, 302, 402, 904, 1102, 1206) despite large dynamic changes in cell resistance during the process.
摘要翻译：使用至少一个恒流源（114,404）的系统和方法来促进对有机存储器单元（102,302,402,904,1102,1206）的编程

5. 发明申请

WO2007064334A1 POLYMER-BASED TRANSISTOR DEVICES, METHODS, AND SYSTEMS 审中-公开
标题翻译：基于聚合物的晶体管器件，方法和系统
公开(公告)号：WO2007064334A1
公开(公告)日：2007-06-07
申请号：PCT/US2005/043788
申请日：2005-12-02
申请人： ADVANCED MICRO DEVICES, INC. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
发明人： BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
IPC分类号： H01L51/05 , H01L29/786
CPC分类号： H01L51/0512 , H01L51/0508
摘要： Disclosed is a semiconductor transistor device (100) with an annular gate (118) surrounding, at least in part, a channel (110) that conducts current between a first (104) and second (114) source/drain. Also disclosed is a semiconductor transistor device (100) having an annular gate (118) and containing a channel (110) composed of a polymer material. Yet also disclosed is the fabrication of a device utilizing a polymer channel (110) surrounded, at least in part, by an annular gate (118). Further disclosed is a system with a means to control (and/or amplify) current via an annular gate (118) surrounding a channel (110) which conducts current between a first (104) and second (114) source/drain.
摘要翻译：公开了具有环形栅极（118）的半导体晶体管器件（100），该环形栅极至少部分地围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）。还公开了具有环形栅极（118）并且包含由聚合物材料构成的沟道（110）的半导体晶体管器件（100）。还公开了使用至少部分由环形栅极（118）包围的聚合物通道（110）的装置的制造。还公开了一种具有通过围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）的环形栅极（118）来控制（和/或扩大）电流的装置的系统。

6. 发明申请

WO2006071683A1 METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY 审中-公开
标题翻译：存储二极管阵列中编程，读取和擦除存储器二极管的方法
公开(公告)号：WO2006071683A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/046406
申请日：2005-12-20
申请人： SPANSION LLC , BILL, Colin, S. , KAZA, Swaroop , FANG, Tzu-Ning , SPITZER, Stuart
发明人： BILL, Colin, S. , KAZA, Swaroop , FANG, Tzu-Ning , SPITZER, Stuart
IPC分类号： G11C16/10
CPC分类号： G11C11/36
摘要： A memory array (140) includes first and second sets of conductors (142), (144) and a plurality of memory-diodes (130), each connecting in a forward direction a conductor (BL) of the first set (142) with a conductor (WL) of the second set (144). An electrical potential is applied across a selected memory-diode (130), from higher to lower potential in the forward direction, intended to program the selected memory-diode (130). During this intended programming, each other memory-diode (130) in the array (140) has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode (130) can be established by applying an electrical potential across that memory-diode (130) from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array (140), problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列（140）包括第一和第二组导体（142），（144）和多个存储器二极管（130），每个存储器二极管（130）在前向方向上与第一组（142）的导体（BL）第二组（144）的导体（WL）。在所选择的存储器二极管（130）上施加电势，从正向上的较高电位到较低的电位，用于对所选择的存储器二极管（130）进行编程。在该期望的编程期间，阵列（140）中的每个其它存储器二极管（130）在其正向方向上提供了低于其阈值电压的电位。每个存储二极管（130）的阈值电压可以通过在该存储二极管（130）上施加从相反方向的较高电位到较低电位的电位来建立。通过这样建立足够的阈值电压，并且通过选择施加到阵列（140）的导体的适当电势，避免了与电流泄漏和干扰有关的问题。

7. 发明申请

WO2006130438A1 PAGE BUFFER ARCHITECTURE FOR PROGRAMMING, ERASING AND READING NANOSCALE RESISTIVE MEMORY DEVICES 审中-公开
标题翻译：用于编程，擦除和读取纳米电阻存储器件的页面缓冲器架构
公开(公告)号：WO2006130438A1
公开(公告)日：2006-12-07
申请号：PCT/US2006/020326
申请日：2006-05-26
申请人： SPANSION LLC , BILL, Colin, S. , CAI, Wei, Daisy
发明人： BILL, Colin, S. , CAI, Wei, Daisy
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1051 , G11C7/106 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2013/0085 , G11C2207/2245
摘要： In the present method of programming and erasing the resistive memory devices (30) of an array thereof, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices (30) whose state is to be changed from the previous state thereof.
摘要翻译：在目前的编程和擦除其阵列的电阻式存储器件（30）的方法中，通过单个命令，在编程和擦除功能中都提供高电流，以仅对那些状态为从之前的状态改变。

8. 发明申请

WO2006102391A3 TEMPERATURE COMPENSATION OF THIN FILM DIODE VOLTAGE THRESHOLD IN MEMORY SENSING CIRCUIT 审中-公开
公开(公告)号：WO2006102391A3
公开(公告)日：2006-09-28
申请号：PCT/US2006/010364
申请日：2006-03-22
申请人： SPANSION LLC , BILL, Colin, S. , CAI, Wei, Daisy
发明人： BILL, Colin, S. , CAI, Wei, Daisy
IPC分类号： G11C7/04 , G11C13/02
摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit (408) and an array core (500) with a temperature variable select device (430). The array core (500) can consist of a thin film diode (430) in series with a nanoscale resistive memory cell (440). The temperature sensitive bias circuit (600) can include a thin film diode (630) in series with two resistors (610, 620) and provides a temperature compensating bias voltage (640) to the array core. The thin film diode (630) of the temperature sensitive bias circuit (600) tracks the diode (430) of the array core (500), while the two resistors (610, 620) create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core (500). The compensating bias reference voltage (640) is generated by the temperature sensitive bias circuit (600), duplicated by a differential amplifier (450), and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell (440).

9. 发明申请

WO2006029280A1 VERTICAL JFET AS USED FOR SELECTIVE COMPONENT IN A MEMORY ARRAY 审中-公开
标题翻译：用于存储阵列中选择性组件的垂直JFET
公开(公告)号：WO2006029280A1
公开(公告)日：2006-03-16
申请号：PCT/US2005/032027
申请日：2005-09-07
申请人： SPANSION LLC , BILL, Colin, S. , VANBUSKIRK, Michael, A.
发明人： BILL, Colin, S. , VANBUSKIRK, Michael, A.
IPC分类号： H01L27/10 , H01L27/098
CPC分类号： H01L27/10 , H01L27/098
摘要： Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell (602) in a memory array while increasing device density in the memory cell array. A vertical JFET (400, 500, 604, 700, 800, 900) is described to which voltages can be selectively applied to control internal current flow there through, which in turn can be employed to manipulate the state of a polymer memory cell (602) coupled to the vertical JFET (400, 500, 604, 700, 800, 900). By mitigating gaps between gates (402, 504, 606, 704, 804, 906), or wordlines (606, 906), and drains (404, 506, 706, 806) of the vertical JFETs (400, 500, 604, 700, 800, 900), feature size can be reduced to permit increased device density. Furthermore, vertical JFETs (400, 500, 604, 700, 800, 900) in the array can be coupled to gates (402, 504, 606, 704, 804, 906) on only two opposite sides, permitting the JFETs (400, 500, 604, 700, 800, 900) to be arranged without gate crossbars between them, further increasing device density. In this manner, the present invention provides switching characteristics to a memory cell and overcomes problematic bulkiness associated with conventional MOS devices.
摘要翻译：公开了系统和方法，其有助于提供存储器阵列中的聚合物存储器单元（602）的选择性功能，同时增加存储器单元阵列中的器件密度。描述了可以选择性地施加电压以控制其中的内部电流的垂直JFET（400,500,600,700,800,900），其可以用于操纵聚合物存储器单元（602 ）耦合到垂直JFET（400,500,600,700,800,900）。通过减轻垂直JFET（400,500,604,700）的门（402,504,606,704,806）或字线（606,906）和漏极（404,506,706,806）之间的间隙，800,900），可以减小特征尺寸以允许增加装置密度。此外，阵列中的垂直JFET（400,500,604,700,800,900）可以仅在两个相对侧耦合到栅极（402,504,606,704,804,906），从而允许JFET（400， 500,604,700,800,900），以便在它们之间没有栅极交叉杆，从而进一步增加了器件密度。以这种方式，本发明向存储器单元提供开关特性，并且克服了与常规MOS器件相关的有问题的体积性。

10. 发明申请

WO2004102579A1 ERASING AND PROGRAMMING AN ORGANIC MEMORY DEVICE AND METHODS OF OPERATING AND FABRICATING 审中-公开
标题翻译：擦除和编程有机存储器件及其操作和制作方法
公开(公告)号：WO2004102579A1
公开(公告)日：2004-11-25
申请号：PCT/US2004/011811
申请日：2004-04-16
申请人： ADVANCED MICRO DEVICES, INC. , LAN, Zhida , BILL, Colin, S. , VANBUSKIRK, Michael, A.
发明人： LAN, Zhida , BILL, Colin, S. , VANBUSKIRK, Michael, A.
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0009 , G11C13/0016 , G11C2213/15 , G11C2213/56 , G11C2213/71
摘要： An organic memory cell (100, 1300, 1500) made of two electrodes (104, 110, 1304, 1306, 1502, 1504) with a selectively conductive media (106/108, 1308) between the two electrodes (104, 110, 1304, 1306, 1502, 1504) is disclosed. The selectively conductive media (106/108, 1308) contains an organic layer (108, 300, 400, 500) and passive layer (106, 200). The selectively conductive media (106/108, 1308) is programmed by applying bias voltages that program a desired impedance state (1301, 1302, 1303) for a memory cell (100, 1300, 1500). The desired impedance state (1301, 1302, 1303) represents one or more bits of information and the memory cell (100, 1300, 1500) does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media (106/108, 1308) is read by applying a current and reading the impedance of the media (106/108, 1308) in order to determine the impedance state (1301, 1302, 1303) of the memory cell (100, 1300, 1500). Methods of making the organic memory devices/cells (100, 1300, 1500), methods of using the organic memory devices/cells (100, 1300, 1500), and devices such as computers containing the organic memory devices/cells (100, 1300, 1500) are also disclosed.
摘要翻译：由两个电极（104,110,1304,1306,1502,1504）制成的有机存储单元（100,1300,1500）在两个电极（104,110,1304）之间具有选择性导电介质（106/108,1308），1306,1502,1504）。选择性导电介质（106/108,1308）包含有机层（108,300,400,500）和无源层（106,200）。选择性导电介质（106/108,1308）通过施加用于存储单元（100,1300,1500）编程期望的阻抗状态（1301,1301,1303）的偏压来编程。期望的阻抗状态（1301,1301,1303）表示一个或多个信息位，并且存储单元（100,1300,1500）不需要恒定的功率或刷新周期来保持所需的阻抗状态。此外，通过施加电流并读取介质（106/108,1308）的阻抗来读取选择性导电介质（106/108,1308），以便确定存储器的阻抗状态（1301,1301,1303）细胞（100,1300,1500）。制造有机存储器件/单元（100,1300,1500）的方法，使用有机存储器件/单元（100,1300,1500）的方法以及诸如包含有机存储器件/单元（100,1300）的计算机，1500）也被公开。

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