专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012178199A2 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS 审中-公开
标题翻译：具有两个终端记忆细胞的记忆阵列结构
公开(公告)号：WO2012178199A2
公开(公告)日：2012-12-27
申请号：PCT/US2012/044077
申请日：2012-06-25
申请人： NAZARIAN, Hagop , CROSSBAR, INC.
发明人： NAZARIAN, Hagop
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C11/1659 , G11C8/14 , G11C11/1653 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2213/33 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
摘要翻译：非易失性存储器件包括沿着第一方向延伸的字线; 沿第二方向延伸的位线; 具有耦合到位线的读取晶体管，至少一个两端存储单元和选择晶体管的存储单元，所述双端存储单元具有耦合到字线的第一端和耦合到栅极的第二端的读取晶体管。两端存储单元的第二端耦合到由选择晶体管的漏极和读取晶体管的栅极共享的公共节点。

2. 发明申请

WO2012178199A3 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS 审中-公开
标题翻译：具有两个终端记忆细胞的记忆阵列结构
公开(公告)号：WO2012178199A3
公开(公告)日：2013-04-18
申请号：PCT/US2012044077
申请日：2012-06-25
申请人： NAZARIAN HAGOP , CROSSBAR INC
发明人： NAZARIAN HAGOP
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C11/1659 , G11C8/14 , G11C11/1653 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2213/33 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
摘要翻译：非易失性存储器件包括沿着第一方向延伸的字线; 沿第二方向延伸的位线; 具有耦合到位线的读取晶体管，至少一个两端存储单元和选择晶体管的存储单元，所述双端存储单元具有耦合到字线的第一端和耦合到栅极的第二端的读取晶体管。两端存储单元的第二端耦合到由选择晶体管的漏极和读取晶体管的栅极共享的公共节点。

3. 发明申请

WO2011159705A3 WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：WO2011159705A3
公开(公告)日：2012-04-19
申请号：PCT/US2011040362
申请日：2011-06-14
申请人： CROSSBAR INC , NAZARIAN HAGOP , JO SUNG HYUN
发明人： NAZARIAN HAGOP , JO SUNG HYUN
IPC分类号： G11C13/00 , G11C16/10 , G11C16/14 , G11C16/34
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

4. 发明申请

WO2007123987A2 NAND ERASE BLOCK SIZE TRIMMING APPARATUS AND METHOD 审中-公开
标题翻译： NAND擦除块大小修整设备和方法
公开(公告)号：WO2007123987A2
公开(公告)日：2007-11-01
申请号：PCT/US2007009553
申请日：2007-04-19
申请人： MICRON TECHNOLOGY INC , NAZARIAN HAGOP A , ROOHPARVAR FRANKIE F
发明人： NAZARIAN HAGOP A , ROOHPARVAR FRANKIE F
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16
摘要： A NAND architecture includes a large NAND string sub-divided into smaller sub¬ strings for erasure, the string subdivided by a plurality of separator elements placed in series with the memory cells of the string, allowing for smaller erase blocks while maintaining the size of the string. The separator elements can be pass transistors or non-volatile or flash memory cells.
摘要翻译： NAND架构包括被分为更小的用于擦除的子串的大NAND串，该字符串由与串的存储单元串联放置的多个分隔元件细分，允许更小的擦除块，同时保持串。分离器元件可以是通过晶体管或非易失性或闪存单元。

5. 发明申请

WO2006124352A3 DEVICES FOR PROGRAMMING A MEMORY 审中-公开
公开(公告)号：WO2006124352A3
公开(公告)日：2006-11-23
申请号：PCT/US2006/017636
申请日：2006-05-08
申请人： MICRON TECHNOLOGY, INC. , NGUYEN, Dzung, H. , LOUIE, Benjamin , NAZARIAN, Hagop, A. , YIP, Aaron , HAN, Jin-Man
发明人： NGUYEN, Dzung, H. , LOUIE, Benjamin , NAZARIAN, Hagop, A. , YIP, Aaron , HAN, Jin-Man
IPC分类号： G11C16/10
摘要： A target memory cell of a memory device (100) is programmed by applying a programming voltage (324, 336, 342) to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage (334, 340) if it is determined that the target memory cell is not programmed. An initial programming voltage (324) and the step voltage are each selectable after fabrication of the memory device.

6. 发明申请

WO2013019678A2 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 审中-公开
标题翻译：利用两端非易失性存储器的现场可编程门阵列
公开(公告)号：WO2013019678A2
公开(公告)日：2013-02-07
申请号：PCT/US2012048712
申请日：2012-07-27
申请人： CROSSBAR INC , NAZARIAN HAGOP , NGUYEN SANG THANH , KUMAR TANMAY
发明人： NAZARIAN HAGOP , NGUYEN SANG THANH , KUMAR TANMAY
IPC分类号： H03K19/173 , G11C13/00
CPC分类号： G11C13/0007 , H03K19/02 , H03K19/17728
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
摘要翻译：这里描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。 RRAM存储单元可以形成在信号输入线和信号输出线的相应交点处。 RRAM存储器单元可以包括分压器，该分压器包括跨越FPGA的VCC和VSS电串联布置的多个可编程电阻元件。分压器的公共节点驱动被配置为激活或去激活交叉点的传输门晶体管的栅极。所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速编程速度，抗辐射性，快速上电以及FPGA技术的显着益处。

7. 发明申请

WO2011159705A2 WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：WO2011159705A2
公开(公告)日：2011-12-22
申请号：PCT/US2011/040362
申请日：2011-06-14
申请人： CROSSBAR, INC. , NAZARIAN, Hagop , JO, Sung, Hyun
发明人： NAZARIAN, Hagop , JO, Sung, Hyun
IPC分类号： G11C13/00 , G11C16/34 , G11C16/10 , G11C16/14
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

8. 发明申请

WO2012047365A1 CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR 审中-公开
标题翻译：电流读出电路及其方法
公开(公告)号：WO2012047365A1
公开(公告)日：2012-04-12
申请号：PCT/US2011/046036
申请日：2011-07-29
申请人： CROSSBAR, INC. , KUO, Harry , NAZARIAN, Hagop
发明人： KUO, Harry , NAZARIAN, Hagop
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C13/0004 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2207/005 , G11C2213/15 , G11C2213/78
摘要： A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation.
摘要翻译：非易失性存储器件包括以阵列提供的多个存储器单元，每个存储器单元具有多个电阻存储器单元和本地字线。每个电阻式存储器单元具有第一端和第二端，每个存储器单元的电阻性存储器单元的第二端耦合到相应存储器单元的本地字线。提供多个位线，每个位线耦合到电阻存储单元之一的第一端。提供了多个选择晶体管，每个选择晶体管被分配给存储器单元中的一个并且具有耦合到所分配的存储器单元的本地字线的漏极端子。提供第一和第二全局字线，每个全局字线耦合到至少一个选择晶体管的控制端。提供第一和第二源极线，每个源极线耦合到至少一个选择晶体管的源极端子。存储器件被配置为同时读出为读操作选择的存储器单元之一中的所有电阻存储器单元。

9. 发明申请

WO2009058563A1 NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY 审中-公开
标题翻译：非易失性存储器阵列分区结构和使用同一存储器中的单级电池和多级电池的方法
公开(公告)号：WO2009058563A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/079969
申请日：2008-10-15
申请人： SPANSION LLC , NAZARIAN, Hagop , POURKERAMATI, Ali
发明人： NAZARIAN, Hagop , POURKERAMATI, Ali
IPC分类号： G11C11/56 , G11C8/06
CPC分类号： G11C11/5621 , G11C16/08 , G11C2211/5641
摘要： A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
摘要翻译：公开了一种存储器件，并且包括存储器单元阵列和配置成以单级单元模式寻址阵列的第一部分的分区系统，以及以多级单元模式的阵列的第二部分。

10. 发明申请

WO2008027681A2 NON-VOLATILE MEMORY DEVICE AND METHOD HAVING BIT-STATE ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING 审中-公开
标题翻译：非易失性存储器件和具有选择最小化信号耦合的位状态分配的方法
公开(公告)号：WO2008027681A2
公开(公告)日：2008-03-06
申请号：PCT/US2007/074867
申请日：2007-07-31
申请人： MICRON TECHNOLOGY, INC. , NAZARIAN, Hagop A.
发明人： NAZARIAN, Hagop A.
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5641 , G11C2211/5643 , G11C2211/5647
摘要： A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the cells in a row using a set of bit state assignments chosen by evaluating data that are to be written to the cells in the row. The control logic unit performs this evaluation by determining the number of cells in the row that will be programmed to each of a plurality of bit states corresponding to the write data. The control logic unit then selects a set of bit state assignments that will cause the programming level assigned to each bit state to be inversely proportional to the number of memory cells in the row that are programmed with the bit state. The selected set of bit states is then used to program the memory cells in the row.
摘要翻译：非易失性存储器件以使寄生信号的耦合最小化的方式对每行中的存储器单元进行编程。控制逻辑单元使用通过评估要写入行中的单元的数据而选择的一组位状态分配来对行中的单元进行编程。控制逻辑单元通过确定将被编程到与写入数据相对应的多个位状态中的每一个的行中的单元数目来执行该评估。然后，控制逻辑单元选择一组位状态分配，这将使得分配给每个位状态的编程电平成为与位状态编程的行中的存储单元的数量成反比。所选择的位状态集合然后用于对行中的存储器单元进行编程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式