专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006124352A3 DEVICES FOR PROGRAMMING A MEMORY 审中-公开
公开(公告)号：WO2006124352A3
公开(公告)日：2006-11-23
申请号：PCT/US2006/017636
申请日：2006-05-08
申请人： MICRON TECHNOLOGY, INC. , NGUYEN, Dzung, H. , LOUIE, Benjamin , NAZARIAN, Hagop, A. , YIP, Aaron , HAN, Jin-Man
发明人： NGUYEN, Dzung, H. , LOUIE, Benjamin , NAZARIAN, Hagop, A. , YIP, Aaron , HAN, Jin-Man
IPC分类号： G11C16/10
摘要： A target memory cell of a memory device (100) is programmed by applying a programming voltage (324, 336, 342) to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage (334, 340) if it is determined that the target memory cell is not programmed. An initial programming voltage (324) and the step voltage are each selectable after fabrication of the memory device.

2. 发明申请

WO2007123987A3 NAND ERASE BLOCK SIZE TRIMMING APPARATUS AND METHOD 审中-公开
公开(公告)号：WO2007123987A3
公开(公告)日：2007-11-01
申请号：PCT/US2007/009553
申请日：2007-04-19
申请人： MICRON TECHNOLOGY, INC. , NAZARIAN, Hagop, A. , ROOHPARVAR, Frankie, F.
发明人： NAZARIAN, Hagop, A. , ROOHPARVAR, Frankie, F.
IPC分类号： G11C16/04
摘要： A NAND architecture includes a large NAND string sub-divided into smaller sub-strings for erasure, the string subdivided by a plurality of separator elements placed in series with the memory cells of the string, allowing for smaller erase blocks while maintaining the size of the string. The separator elements can be pass transistors or non-volatile or flash memory cells.

3. 发明申请

WO2005029501A1 BOOSTED SUBSTRATE/TUB PROGRAMMING FOR FLASH MEMORIES 审中-公开
标题翻译：用于闪存存储器的增强基板/ TUB编程
公开(公告)号：WO2005029501A1
公开(公告)日：2005-03-31
申请号：PCT/US2004/030014
申请日：2004-09-14
申请人： MICRON TECHNOLOGY, INC. , NAZARIAN, Hagop, A.
发明人： NAZARIAN, Hagop, A.
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C16/0483
摘要： A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate "tub" of a NAND Flash memory array to precharge a channel of carriers within the floating gate memory cells prior to applying a high gate programming voltage to the gate of the selected floating gate memory cells and coupling a program or program-inhibit voltage to program the selected floating gate memory cell(s) as desired. The use of a boosted tub programming approach avoids the requirement that the bitline and/or source line circuit design of the NAND Flash array be able to withstand or carry high voltages during programming of a floating gate memory cells and allows reuse of the block erase high voltage circuits connected to the substrate tub. This allows the NAND Flash memory array to be designed with smaller circuit designs and/or smaller circuit feature elements.
摘要翻译：描述了一种升压的衬底槽/衬底浮动栅极存储单元编程过程，其将电压施加到NAND闪存阵列的衬底或衬底“桶”，以在施加高栅极之前对浮置栅极存储器单元中的载流子通道预充电编程电压到所选择的浮动栅极存储器单元的栅极，并且耦合程序或程序禁止电压以根据需要对所选择的浮动栅极存储单元进行编程。使用升压桶编程方法避免了NAND闪存阵列的位线和/或源极线电路设计在浮置栅极存储器单元的编程期间能够承受或承载高电压，并允许重新使用块擦除高电平连接到衬底桶的电压电路。这允许NAND闪存阵列被设计成具有更小的电路设计和/或更小的电路特征元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式