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1. 发明申请

WO2012047365A1 CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR 审中-公开
标题翻译：电流读出电路及其方法
公开(公告)号：WO2012047365A1
公开(公告)日：2012-04-12
申请号：PCT/US2011/046036
申请日：2011-07-29
申请人： CROSSBAR, INC. , KUO, Harry , NAZARIAN, Hagop
发明人： KUO, Harry , NAZARIAN, Hagop
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C13/0004 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2207/005 , G11C2213/15 , G11C2213/78
摘要： A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation.
摘要翻译：非易失性存储器件包括以阵列提供的多个存储器单元，每个存储器单元具有多个电阻存储器单元和本地字线。每个电阻式存储器单元具有第一端和第二端，每个存储器单元的电阻性存储器单元的第二端耦合到相应存储器单元的本地字线。提供多个位线，每个位线耦合到电阻存储单元之一的第一端。提供了多个选择晶体管，每个选择晶体管被分配给存储器单元中的一个并且具有耦合到所分配的存储器单元的本地字线的漏极端子。提供第一和第二全局字线，每个全局字线耦合到至少一个选择晶体管的控制端。提供第一和第二源极线，每个源极线耦合到至少一个选择晶体管的源极端子。存储器件被配置为同时读出为读操作选择的存储器单元之一中的所有电阻存储器单元。

2. 发明申请

WO2012178199A2 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS 审中-公开
标题翻译：具有两个终端记忆细胞的记忆阵列结构
公开(公告)号：WO2012178199A2
公开(公告)日：2012-12-27
申请号：PCT/US2012/044077
申请日：2012-06-25
申请人： NAZARIAN, Hagop , CROSSBAR, INC.
发明人： NAZARIAN, Hagop
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C11/1659 , G11C8/14 , G11C11/1653 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2213/33 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
摘要翻译：非易失性存储器件包括沿着第一方向延伸的字线; 沿第二方向延伸的位线; 具有耦合到位线的读取晶体管，至少一个两端存储单元和选择晶体管的存储单元，所述双端存储单元具有耦合到字线的第一端和耦合到栅极的第二端的读取晶体管。两端存储单元的第二端耦合到由选择晶体管的漏极和读取晶体管的栅极共享的公共节点。

3. 发明申请

WO2011159705A2 WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：WO2011159705A2
公开(公告)日：2011-12-22
申请号：PCT/US2011/040362
申请日：2011-06-14
申请人： CROSSBAR, INC. , NAZARIAN, Hagop , JO, Sung, Hyun
发明人： NAZARIAN, Hagop , JO, Sung, Hyun
IPC分类号： G11C13/00 , G11C16/34 , G11C16/10 , G11C16/14
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

4. 发明申请

WO2013019678A3 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 审中-公开
公开(公告)号：WO2013019678A3
公开(公告)日：2013-02-07
申请号：PCT/US2012/048712
申请日：2012-07-27
申请人： CROSSBAR, INC. , NAZARIAN, Hagop , NGUYEN, Sang Thanh , KUMAR, Tanmay
发明人： NAZARIAN, Hagop , NGUYEN, Sang Thanh , KUMAR, Tanmay
IPC分类号： H03K19/173 , G11C13/00
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

5. 发明申请

WO2009058563A1 NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY 审中-公开
标题翻译：非易失性存储器阵列分区结构和使用同一存储器中的单级电池和多级电池的方法
公开(公告)号：WO2009058563A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/079969
申请日：2008-10-15
申请人： SPANSION LLC , NAZARIAN, Hagop , POURKERAMATI, Ali
发明人： NAZARIAN, Hagop , POURKERAMATI, Ali
IPC分类号： G11C11/56 , G11C8/06
CPC分类号： G11C11/5621 , G11C16/08 , G11C2211/5641
摘要： A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
摘要翻译：公开了一种存储器件，并且包括存储器单元阵列和配置成以单级单元模式寻址阵列的第一部分的分区系统，以及以多级单元模式的阵列的第二部分。

6. 发明申请

WO2016126838A1 A NODE RETAINER CIRCUIT INCORPORATING RRAM 审中-公开
标题翻译：节点保持器电路并入RRAM
公开(公告)号：WO2016126838A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/016396
申请日：2016-02-03
申请人： CROSSBAR, INC.
发明人： ASNAASHARI, Mehdi , NAZARIAN, Hagop
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/004 , G11C14/009
摘要： A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.
摘要翻译：提供保持器节点电路，其可保持电子装置的易失性电路元件（例如，触发器，锁存器，开关，寄存器等）的状态信息以用于计划或未计划的电力下行事件。保持器节点电路可以包括非易失性的电阻切换存储器单元，具有非常快的读取和写入性能。与功率管理电路相耦合，保持器节点电路可被激活以接收和存储由易失性电路元件输出的信号（例如，比特），并被激活以输出所存储的信号。各种实施例公开了用于计划的关闭事件以及意外关闭事件的状态信息的非易失性保留。在数十纳秒的读写速度下，可为较长时间帧应用的时钟周期之间的易失性电路元件提供休眠模式，从而实现活动时段之间的间歇断电事件。这可以降低功耗而不会损失电子设备的活动。

7. 发明申请

WO2022197307A1 METHODS AND APPARATUS FOR FACILITATED PROGRAM AND ERASE OF TWO-TERMINAL MEMORY DEVICES 审中-公开
公开(公告)号：WO2022197307A1
公开(公告)日：2022-09-22
申请号：PCT/US2021/023154
申请日：2021-03-19
申请人： CROSSBAR, INC.
发明人： NAZARIAN, Hagop , NGUYEN, Sang
IPC分类号： G11C13/00
摘要： A method for facilitating erase or program operations on two-terminal memory devices includes substantially simultaneously initiating erase cycle or program cycle for two-terminal memory devices from a first plurality of two-terminal memory devices, monitoring erase detect or program detect conditions for each of the two-terminal memory devices, and before detecting erase detect or program detect conditions for all of the two-terminal memory devices, the method includes detecting an erase detect or a program detect condition for the first two-terminal memory device from the first plurality of two-terminal memory devices, and initiating an erase cycle or a program for a second two-terminal memory device for a second plurality of two-terminal memory devices, in response to detecting the erase detect or program detect condition for the first two-terminal memory device.

8. 发明申请

WO2021207224A1 DISTINCT CHIP IDENTIFIER UTILIZING UNCLONABLE CHARACTERISTICS OF ON-CHIP RESISTIVE MEMORY ARRAY 审中-公开
公开(公告)号：WO2021207224A1
公开(公告)日：2021-10-14
申请号：PCT/US2021/025994
申请日：2021-04-06
申请人： CROSSBAR, INC.
发明人： JO, Sung Hyun , NAZARIAN, Hagop , NGUYEN, Sang , GUY, Jeremy , LI, Zhi
IPC分类号： H01L27/24 , H01L45/00 , H04L9/00
摘要： A semiconductor device is disclosed which comprises a plurality of two-terminal resistive switching devices (420), wherein an electrode (322) in contact with a resistive switching layer (324) has a root mean square surface roughness (425, 427) greater than 2 nm, and a native characteristic of two of the resistive switching devices has a correlation coefficient within a range of -0.1 to 0.1. The stochastic physical characteristics of the resistive switching devices on a semiconductor chip can be utilized for generating distinct data for electronic identification for that semiconductor chip, for verification of communications with the semiconductor chip or for generating cryptographic keys.

9. 发明申请

WO2015130699A1 NAND ARRAY COMPRISING PARALLEL TRANSISTOR AND TWO-TERMINAL SWITCHING DEVICE 审中-公开
标题翻译：包括并联晶体管和两端开关器件的NAND阵列
公开(公告)号：WO2015130699A1
公开(公告)日：2015-09-03
申请号：PCT/US2015/017360
申请日：2015-02-24
申请人： CROSSBAR, INC.
发明人： NAZARIAN, Hagop
IPC分类号： H01L47/00
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/56 , G11C11/5607 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/003 , G11C13/0069 , G11C2213/75 , H01L27/2436 , H01L27/2463
摘要： Providing for a high performance and efficiency NAND architecture is described herein. By way of example, a NAND array is disclosed comprising memory cells having a 1 transistor - 1 two-terminal memory device (IT-1D) arrangement. Memory cells of the NAND array can be arranged electrically in serial with respect to each other, from source to drain. Moreover, respective memory cells comprise a transistor component connected in parallel to a two-terminal memory device. In some embodiments, a resistance of the activated transistor component is selected to be substantially less than that of the two-terminal memory device, and the resistance of the deactivated transistor component is selected to be substantially higher than the two-terminal memory device. Accordingly, by activating or deactivating the transistor component, a signal applied to the memory cell can be shorted past the two-terminal memory device, or directed through the two-terminal memory device, respectively.
摘要翻译：本文描述了提供高性能和高效率的NAND架构。作为示例，公开了一种NAND阵列，其包括具有1晶体管1两端存储器件（IT-1D）布置的存储器单元。 NAND阵列的存储单元可以相对于彼此串联地从源极到漏极布置。此外，各个存储单元包括并联连接到两端存储器件的晶体管组件。在一些实施例中，激活的晶体管部件的电阻被选择为基本上小于两端存储器件的电阻，并且去激活的晶体管部件的电阻被选择为显着高于两端存储器件。因此，通过激活或去激活晶体管组件，施加到存储单元的信号可以分别通过两端存储器件短路，或通过两端存储器件引导。

10. 发明申请

WO2013177566A1 HIGH OPERATING SPEED RESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：高操作速度随机访问存储器
公开(公告)号：WO2013177566A1
公开(公告)日：2013-11-28
申请号：PCT/US2013/042746
申请日：2013-05-24
申请人： CROSSBAR, INC.
发明人： NGUYEN, Sang , NAZARIAN, Hagop
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/419 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0097 , G11C2013/0042 , G11C2013/0052 , G11C2213/53 , G11C2213/74 , G11C2213/78 , G11C2213/79
摘要： Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance of the bitline). With this arrangement, a signal applied at the bitline can quickly switch the transistor gate, in response to the RRAM memory being in a conductive state. A sensing circuit configured to measure the transistor can detect a change in current, voltage, etc., of the transistor and determine a state of the RRAM memory from the measurement. Moreover, this measurement can occur very quickly due to the low capacitance of the transistor gate, greatly improving the read speed of RRAM.
摘要翻译：本文描述了提供具有高读速度的电阻随机存取存储器（RRAM）。作为示例，RRAM存储器可以通过位线在一个端子供电，并且在另一个端子处连接到具有低栅极电容（相对于位线的电容）的晶体管的栅极。利用这种布置，响应于RRAM存储器处于导通状态，施加在位线处的信号可以快速地切换晶体管栅极。配置为测量晶体管的感测电路可以检测晶体管的电流，电压等的变化，并从测量确定RRAM存储器的状态。此外，由于晶体管栅极的低电容，该测量可能非常快地发生，极大地提高了RRAM的读取速度。

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