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1. 发明申请

WO2013019678A2 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 审中-公开
标题翻译：利用两端非易失性存储器的现场可编程门阵列
公开(公告)号：WO2013019678A2
公开(公告)日：2013-02-07
申请号：PCT/US2012048712
申请日：2012-07-27
申请人： CROSSBAR INC , NAZARIAN HAGOP , NGUYEN SANG THANH , KUMAR TANMAY
发明人： NAZARIAN HAGOP , NGUYEN SANG THANH , KUMAR TANMAY
IPC分类号： H03K19/173 , G11C13/00
CPC分类号： G11C13/0007 , H03K19/02 , H03K19/17728
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
摘要翻译：这里描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。 RRAM存储单元可以形成在信号输入线和信号输出线的相应交点处。 RRAM存储器单元可以包括分压器，该分压器包括跨越FPGA的VCC和VSS电串联布置的多个可编程电阻元件。分压器的公共节点驱动被配置为激活或去激活交叉点的传输门晶体管的栅极。所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速编程速度，抗辐射性，快速上电以及FPGA技术的显着益处。

2. 发明申请

WO2012178199A3 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS 审中-公开
标题翻译：具有两个终端记忆细胞的记忆阵列结构
公开(公告)号：WO2012178199A3
公开(公告)日：2013-04-18
申请号：PCT/US2012044077
申请日：2012-06-25
申请人： NAZARIAN HAGOP , CROSSBAR INC
发明人： NAZARIAN HAGOP
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C11/1659 , G11C8/14 , G11C11/1653 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2213/33 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
摘要翻译：非易失性存储器件包括沿着第一方向延伸的字线; 沿第二方向延伸的位线; 具有耦合到位线的读取晶体管，至少一个两端存储单元和选择晶体管的存储单元，所述双端存储单元具有耦合到字线的第一端和耦合到栅极的第二端的读取晶体管。两端存储单元的第二端耦合到由选择晶体管的漏极和读取晶体管的栅极共享的公共节点。

3. 发明申请

WO2011159705A3 WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：WO2011159705A3
公开(公告)日：2012-04-19
申请号：PCT/US2011040362
申请日：2011-06-14
申请人： CROSSBAR INC , NAZARIAN HAGOP , JO SUNG HYUN
发明人： NAZARIAN HAGOP , JO SUNG HYUN
IPC分类号： G11C13/00 , G11C16/10 , G11C16/14 , G11C16/34
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

4. 发明申请

WO2016126838A4 A NODE RETAINER CIRCUIT INCORPORATING RRAM 审中-公开
标题翻译：节点保护器电路
公开(公告)号：WO2016126838A4
公开(公告)日：2016-10-13
申请号：PCT/US2016016396
申请日：2016-02-03
申请人： CROSSBAR INC
发明人： ASNAASHARI MEHDI , NAZARIAN HAGOP
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/004 , G11C14/009
摘要： A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an electronic device for planned or unplanned power-down events. The retainer node circuit can include a resistive-switching memory cell that is nonvolatile, having very fast read and write performance. Coupled with power management circuitry, the retainer node circuit can be activated to receive and store a signal (e.g., bit) output by the volatile circuit element, and activated to output the stored signal. Various embodiments disclose non-volatile retention of state information for planned shut-down events as well as unplanned shut-down events. With read and write speeds in the tens of nanoseconds, sleep mode can be provided for volatile circuit elements between clock cycles of longer time-frame applications, enabling intermittent power-down events between active periods. This enables reduction in power without loss of activity for an electronic device.
摘要翻译：提供了一种保持器节点电路，其可以保留用于计划或非计划掉电事件的电子设备的易失性电路元件（例如，触发器，锁存器，开关，寄存器等）的状态信息。保持器节点电路可以包括非易失性的电阻式切换存储单元，具有非常快的读和写性能。与电源管理电路耦合，保持器节点电路可以被激活以接收和存储由易失性电路元件输出的信号（例如，位），并被激活以输出存储的信号。各种实施例公开了用于计划停机事件的非易失性保留状态信息以及非计划停机事件。在读写速度为几十纳秒的情况下，可以为更长时间帧应用的时钟周期之间的易失性电路元件提供睡眠模式，从而实现活动周期之间的间歇断电事件。这使得能够降低功率而不损失电子设备的活动性。

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