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51. 发明申请

WO2012154240A1 MEMORY INTERFACE WITH SELECTABLE EVALUATION MODES 审中-公开
标题翻译：具有可选择评估模式的记忆界面
公开(公告)号：WO2012154240A1
公开(公告)日：2012-11-15
申请号：PCT/US2012/025163
申请日：2012-02-15
申请人： CAVIUM, INC. , XANTHOPOULOS, Thucydides , LIN, David
发明人： XANTHOPOULOS, Thucydides , LIN, David
IPC分类号： G11C29/02 , G01R31/28 , G01R31/317 , G06F11/267 , G06F11/27 , G06F11/22 , G11C29/48
CPC分类号： G11C29/02 , G06F11/27 , G11C29/022 , G11C29/48
摘要： A memory interface enables AC characterization under test conditions without requiring the use of automated test equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).
摘要翻译：存储器接口可以在测试条件下进行交流表征，而无需使用自动化测试设备（ATE）和功能模式。存储器控制器可以被配置为通过测试接口生成输出模式，并且使用外部紧张眼随机数发生器和检验器创建用于输入规范测试的回送路径。因此，可以通过测试接口（JTAG）在相对简单的测试设置和测试过程下评估存储器接口的电气和时序规范，而不是在自动测试中建立类似的存储器访问模式的复杂处理器程序设备（ATE）。

52. 发明申请

WO2010065290A2 MEMORY SYSTEM WITH COMMAND FILTERING 审中-公开
标题翻译：带命令过滤的内存系统
公开(公告)号：WO2010065290A2
公开(公告)日：2010-06-10
申请号：PCT/US2009/064813
申请日：2009-11-17
申请人： RAMBUS INC. , WARE, Frederick, A. , RICHARDSON, Wayne , KASAMSETTY, Kishore
发明人： WARE, Frederick, A. , RICHARDSON, Wayne , KASAMSETTY, Kishore
IPC分类号： G06F13/32 , G06F13/24 , G06F11/10 , G06F12/00
CPC分类号： G11C29/56 , G01R31/3171 , G11C29/028 , G11C29/48 , G11C29/50012 , G11C29/56012
摘要： A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.
摘要翻译：存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控制器。定期校准链路的时间和电压裕度，以减少误码。高速请求链接使校准复杂化，因为通过未校准的请求链接发布的命令可能被存储器设备错误地解释。错误解释的命令会破坏校准过程（例如，写入命令可能被错误解释为断电命令）。内存控制器使用单独的低速控制接口来解决此问题，以发出过滤器命令，指示内存设备在校准模式下拒绝潜在的破坏性请求。

53. 发明申请

WO2007022446A3 ELECTRONIC DEVICE HAVING AN INTERFACE SUPPORTED TESTING MODE 审中-公开
标题翻译：具有接口支持测试模式的电子设备
公开(公告)号：WO2007022446A3
公开(公告)日：2009-04-23
申请号：PCT/US2006032416
申请日：2006-08-17
申请人： INAPAC TECHNOLOGY INC , ONG ADRIAN
发明人： ONG ADRIAN
IPC分类号： G01R31/26
CPC分类号： G01R31/318513 , G01R31/31701 , G01R31/3172 , G01R31/31723 , G01R31/319 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H01L2224/05554 , H01L2224/48139
摘要： A system is provided for testing a first integrated circuit chip associated with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test mode.
摘要翻译：提供了一种用于测试与半导体器件中的至少第二集成电路芯片相关联的第一集成电路芯片的系统，其中半导体器件的至少一些外部端子将被第一和第二集成电路芯片共享，并且其中第一个集成电路芯片设计用于正常操作和测试模式。该系统包括多个多路复用器电路。当第一集成电路芯片处于正常操作时，每个复用器电路可操作以从第二集成电路芯片接收相应的信号。当第一集成电路芯片处于测试模式时，每个复用器电路还可操作以从第二集成电路芯片或相关联的外部端子接收相应的信号。半导体器件的外部端子可操作以接收用于使第一集成电路芯片在正常操作和测试模式之间转变的信号。

54. 发明申请

WO2008051932A3 HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE 审中-公开
标题翻译：高速双向数据速率JTAG接口
公开(公告)号：WO2008051932A3
公开(公告)日：2008-09-18
申请号：PCT/US2007082143
申请日：2007-10-22
申请人： TEXAS INSTRUMENTS INC , WHETSEL LEE D
发明人： WHETSEL LEE D
IPC分类号： G06F11/00
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318544 , G01R31/318547 , G11C29/48
摘要： A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
摘要翻译：一种过程和装置提供一种JTAG TAP控制器（302），以使用减少的引脚数，高速DDR接口（202）来访问设备的JTAG TAP域（106）。通过将来自TAP控制器的单独TDI和TMS信号组合成单个信号并在驱动DDR接口的TCK的上升沿和下降沿传送单个信号的TDI和TMS信号来实现接入。 TAP域可以以点对点方式或以可寻址总线方式耦合到TAP控制器。对TAP域的访问可用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

55. 发明申请

WO2008076912A1 METHOD AND DEVICE FOR TESTING MEMORY 审中-公开
标题翻译：用于测试记忆的方法和装置
公开(公告)号：WO2008076912A1
公开(公告)日：2008-06-26
申请号：PCT/US2007/087625
申请日：2007-12-14
申请人： QUALCOMM Incorporated , SHEN, Jian , BASSETT, Paul
发明人： SHEN, Jian , BASSETT, Paul
IPC分类号： G11C29/48
CPC分类号： G11C29/48 , G11C29/1201
摘要： A method of testing a memory is provided that includes initiating a test on a computer readable memory. The computer readable memory provides output data associated with the test. Further, the method includes selecting to receive the output data from a first register or a second register. In a particular embodiment, the method may include selecting to receive the output data from the first register or the second register by use of a control line. In another particular embodiment, the method may include selecting to receive the RAM input data from the first register or the second register by use of a control line. The control line is configured dynamically by hardware or software on cycle by cycle basis. In a particular embodiment, the test is a built-in-self-test (BIST).
摘要翻译：提供了一种测试存储器的方法，其包括在计算机可读存储器上启动测试。计算机可读存储器提供与测试相关联的输出数据。此外，该方法包括选择从第一寄存器或第二寄存器接收输出数据。在特定实施例中，该方法可以包括通过使用控制线来选择从第一寄存器或第二寄存器接收输出数据。在另一特定实施例中，该方法可以包括通过使用控制线来选择从第一寄存器或第二寄存器接收RAM输入数据。控制线由硬件或软件逐周期动态配置。在特定实施例中，测试是内置自检（BIST）。

56. 发明申请

WO2007077849A1 半導体チップ及び半導体集積回路审中-公开
标题翻译：半导体芯片和半导体集成电路
公开(公告)号：WO2007077849A1
公开(公告)日：2007-07-12
申请号：PCT/JP2006/325981
申请日：2006-12-26
申请人：株式会社システム・ファブリケーション・テクノロジーズ , 熊谷浩一
发明人：熊谷浩一
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/31713 , G11C29/1201 , H01L2924/0002 , H01L2924/00
摘要：　本発明の半導体チップは、インターポーザに実装可能な半導体チップであって、最小ピッチ間隔が１００μｍ以下で、前記インターポーザ内の配線と前記半導体チップ内の配線とを接続する複数の電極と、前記複数の電極の一部に接続された複数のプローブ電極と、前記プローブ電極に入力されるテスト信号を分割して、前記半導体チップ内の配線であって前記複数の電極に接続された配線に供給する分割手段と、前記分割手段により分割されたテスト信号に基づいて所定の信号処理を行う信号処理手段と、を備えている。
摘要翻译：提供了可以安装在插入件上的半导体芯片。半导体芯片的最小间距间隔为100μm以下。半导体芯片设置有用于将插入件中的布线与半导体芯片中的布线连接的多个电极; 连接到所述电极的一部分的多个探针电极; 分割装置，用于分割输入到探针电极的测试信号，并将划分的信号提供给半导体芯片中的与电极连接的布线; 以及信号处理装置，用于基于由分割装置分割的测试信号执行规定的信号处理。

57. 发明申请

WO2007044286A2 MEMORY SCAN TESTING 审中-公开
标题翻译：内存扫描测试
公开(公告)号：WO2007044286A2
公开(公告)日：2007-04-19
申请号：PCT/US2006/038354
申请日：2006-10-03
申请人： TEXAS INSTRUMENTS INCORPORATED , GROSE, William, E. , LAMBERT, Lonnie, L. , PITZ, Jeanne, Krayer , TANAKA, Toru
发明人： GROSE, William, E. , LAMBERT, Lonnie, L. , PITZ, Jeanne, Krayer , TANAKA, Toru
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C16/04 , G11C29/48 , G11C2029/3202
摘要： A method is provided for testing a semiconductor device that includes both a digital (310) and analog (320) portion. The digital portion may include a plurality of latch devices (361-364), and the analog portion may include a plurality of memory cells (321) and a plurality of selector devices (325). Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch devices, and is controlled by a selector input (215). A load clock (372) is applied to load a pattern into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock (371) is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.
摘要翻译：提供了一种用于测试包括数字（310）和模拟（320）部分的半导体器件的方法。数字部分可以包括多个锁存装置（361-364），并且模拟部分可以包括多个存储单元（321）和多个选择器装置（325）。多个选择器装置中的每一个电耦合到存储器单元中的相应一个存储器单元，至少间接耦合到多个锁存器装置中的一个，并且由选择器输入（215）控制。加载时钟（372）被用于将图案加载到多个锁存器件中。选择器输入被断言，使得图案的导数被多个选择器接收并返回到多个锁存装置。系统时钟（371）被施加到多个锁存器件，使得图案的导数被加载到多个锁存器件中。

58. 发明申请

WO2007032904A2 SHARED BOND PAD FOR TESTING A MEMORY WITHIN A PACKAGED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：共用粘结垫用于在包装半导体器件中测试存储器
公开(公告)号：WO2007032904A2
公开(公告)日：2007-03-22
申请号：PCT/US2006033731
申请日：2006-08-28
申请人： INAPAC TECHNOLOGY INC , ONG ADRIAN E
发明人： ONG ADRIAN E
IPC分类号： G01R31/26
CPC分类号： G01R31/31723 , G01R31/31701 , G01R31/3172 , G01R31/318513 , G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/3602 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014
摘要： A system is provided for communicating with a device within a packaged semiconductor device through a shared external terminal thereof. As one example, the system provides for testing a memory within the package. In addition to the device and the shared external terminal, the system includes a command register that receives a plurality of command signals, and digital logic devices coupled between the external terminal and the command register. Each of the digital logic devices receives a different clock signal and outputs one of the command signals to the command register. The command signals are provided to the external terminal in a sequence that is coordinated with the clock signals so that each digital logic device buffers one of the command signals.
摘要翻译：提供了一种系统，用于通过其共享的外部终端与封装的半导体器件内的器件进行通信。作为一个例子，系统提供了测试包内的内存。除了设备和共享外部终端之外，系统还包括接收多个命令信号的命令寄存器，以及耦合在外部终端和命令寄存器之间的数字逻辑设备。每个数字逻辑器件接收不同的时钟信号并将其中一个命令信号输出到命令寄存器。命令信号以与时钟信号相协调的顺序被提供给外部终端，使得每个数字逻辑设备缓冲其中一个命令信号。

59. 发明申请

WO2005088644A1 DFT TECHNIQUE FOR STRESSING SELF-TIMED SEMICONDUCTOR MEMORIES TO DETECT DELAY FAULTS 审中-公开
标题翻译：用于压制自身半导体存储器的DFT技术来检测延迟故障
公开(公告)号：WO2005088644A1
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050800
申请日：2005-03-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , U.S. PHILIPS CORPORATION , AZIMANE, Mohamed , MAJHI, Ananta
发明人： AZIMANE, Mohamed , MAJHI, Ananta
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/024 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C29/56012
摘要： The present invention relates to a test system (100) interposed between a clock monitor (152) and an internal memory block (125) of a self-timed memory. In an example embodiment, the test system (100) receives an internal clock signal (104) from the clock monitor (152), an external clock signal (CL) and a control signal (CS). A multiplexer (110) of the test system provides in dependence upon the control signal (CS) the internal clock signal (104) to the internal memory block (125) during a normal mode of operation of the self-timed memory and the external clock signal (CL) to the internal memory block (125) during a test mode (108) of the self-timed memory. The test system (100) enables control of the clock cycle of the internal memory block (125) by directly applying the external clock signal (CL) during test mode. Thus, the internal memory block is stressed properly enabling the detection of small delay faults.
摘要翻译：本发明涉及一种插入在自定时存储器的时钟监视器（152）和内部存储块（125）之间的测试系统（100）。在示例性实施例中，测试系统（100）从时钟监视器（152），外部时钟信号（CL）和控制信号（CS）接收内部时钟信号（104）。在自定时存储器和外部时钟的正常操作模式期间，测试系统的多路复用器（110）根据控制信号（CS）提供内部存储器块（125）的内部时钟信号（104）在自定时存储器的测试模式（108）期间向内部存储器块（125）发送信号（CL）。测试系统（100）通过在测试模式期间直接施加外部时钟信号（CL）来实现内部存储器块（125）的时钟周期的控制。因此，内部存储器块被适当地压缩，能够检测到小的延迟故障。

60. 发明申请

WO2005034176A2 APPARATUS AND METHOD FOR SELECTIVELY CONFIGURING A MEMORY DEVICE USING A BI-STABLE RELAY 审中-公开
标题翻译：使用双稳态继电器选择性地配置存储器件的装置和方法
公开(公告)号：WO2005034176A2
公开(公告)日：2005-04-14
申请号：PCT/US2004/027918
申请日：2004-08-26
申请人： MICRON TECHNOLOGY, INC. , GOMM, Tyler, J.
发明人： GOMM, Tyler, J.
IPC分类号： H01L
CPC分类号： G11C29/883 , G11C7/10 , G11C11/401 , G11C11/4093 , G11C23/00 , G11C29/1201 , G11C29/48 , G11C29/88 , G11C2207/2254
摘要： The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system includes input, output, and data storage devices, a processor coupled to the devices, a memory device coupled to the processor, and a configuration circuit interposed between the processor and the memory device to selectively couple lines in the address, control and data busses of the processor to lines in the address, control and data busses of the memory device. In another embodiment, a memory device includes an array coupleable to one or more busses of an external device and a configuration circuit between the array and the busses of the external device to selectively couple the busses to the memory cell array. In a particular embodiment, the configuration circuit includes one or more bi-stable relays, such as Micro-Electrical-Mechanical System (MEMS) relays.
摘要翻译：本发明公开的实施例包括具有可选存储器容量的半导体存储器装置。在一个实施例中，系统包括输入，输出和数据存储设备，耦合到设备的处理器，耦合到处理器的存储设备，以及插入处理器和存储器设备之间的配置电路，以选择性地耦合地址中的行，处理器的控制和数据总线到存储器件的地址，控制和数据总线中。在另一个实施例中，存储器件包括可耦合到外部设备的一个或多个总线的阵列和阵列与外部设备的总线之间的配置电路，以选择性地将总线连接到存储器单元阵列。在特定实施例中，配置电路包括一个或多个双稳态继电器，例如微机电系统（MEMS）继电器。

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