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1. 发明申请

WO2007050608A3 TESTING AND RECOVERY IN A MULTILAYER DEVICE 审中-公开
公开(公告)号：WO2007050608A3
公开(公告)日：2007-05-03
申请号：PCT/US2006/041481
申请日：2006-10-23
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian , EGAN, Richard
发明人： ONG, Adrian , EGAN, Richard
IPC分类号： G11C29/00
摘要： Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods. The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.

2. 发明申请

WO2011031655A1 METHOD AND SYSTEM FOR PROVIDING A HIERARCHICAL DATA PATH FOR SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY 审中-公开
标题翻译：用于提供转移转矩随机存取存储器的分层数据路径的方法和系统
公开(公告)号：WO2011031655A1
公开(公告)日：2011-03-17
申请号：PCT/US2010/047941
申请日：2010-09-07
申请人： GRANDIS, INC. , ONG, Adrian, E.
发明人： ONG, Adrian, E.
IPC分类号： G11C19/08
CPC分类号： G11C11/16 , G11C7/18 , G11C11/1653 , G11C11/1655 , G11C11/1673 , G11C11/1675 , G11C2207/002
摘要： A method and system for providing a magnetic memory are described. The method and system include providing memory array tiles (MATs), intermediate circuitry, global bit lines, global word lines, and global circuitry. Each MAT includes magnetic storage cells, bit lines, and word lines. Each of the magnetic storage cells includes at least one magnetic element and at least one selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element(s). The bit lines and the word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a first portion of the plurality of MATs. Each global word line corresponds to a second portion of the MATs. The global circuitry selects and drives part of the global bit lines and part of the global word lines for the read and write operations.
摘要翻译：描述了一种用于提供磁存储器的方法和系统。该方法和系统包括提供存储器阵列瓦片（MATs），中间电路，全局位线，全局字线和全局电路。每个MAT包括磁存储单元，位线和字线。每个磁存储单元包括至少一个磁性元件和至少一个选择装置。磁性元件可通过驱动通过磁性元件的写入电流来编程。位线和字线对应于磁存储单元。中间电路控制MAT内的读写操作。每个全局位线对应于多个MAT的第一部分。每个全局字线对应于MAT的第二部分。全局电路选择并驱动部分全局位线和部分全局字线用于读取和写入操作。

3. 发明申请

WO2009126812A1 PROGRAMMABLE MEMORY REPAIR SCHEME 审中-公开
标题翻译：可编程存储器维修方案
公开(公告)号：WO2009126812A1
公开(公告)日：2009-10-15
申请号：PCT/US2009/040079
申请日：2009-04-09
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian, E. , HO, Fan
发明人： ONG, Adrian, E. , HO, Fan
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C11/401 , G11C11/4085 , G11C29/027 , G11C29/04 , G11C29/12 , G11C29/4401 , G11C29/48 , G11C29/78 , G11C29/789 , G11C29/802 , G11C2229/743
摘要： The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.
摘要翻译：本公开提供了用于测试和操作该半导体器件的方法，系统和装置。半导体存储器件包括数据存储元件和修复电路。数据存储元件包括主数据存储元件和一个或多个冗余数据存储元件，主数据存储元件具有用于存储器存取操作的相应地址。修复电路由与存储器件分开的另一个半导体器件可编程，以识别主数据存储元件的故障地址，并且编程的修复电路被配置为将存储器访问从具有识别的故障地址的主数据存储元件重新路由到相应的冗余数据存储元件。

4. 发明申请

WO2007130640A2 MEMORY DEVICE INCLUDING MULTIPLEXED INPUTS 审中-公开
标题翻译：包含多路输入的存储器件
公开(公告)号：WO2007130640A2
公开(公告)日：2007-11-15
申请号：PCT/US2007/010943
申请日：2007-05-04
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian E.
发明人： ONG, Adrian E.
IPC分类号： G11C7/10
CPC分类号： G11C5/066 , G11C8/06
摘要： Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be received at a shared conductor accessible by devices exterior to the semiconductor package and communicated to two contacts on the integrated circuit that are inaccessible to the exterior of the semiconductor package. In various embodiments, signals required to support a full set of features of the JEDEC JESD79E standard or the JEDEC JESD79-2C standard are communicated using a reduced number of exterior contacts.
摘要翻译：描述了用于减少半导体封装上的外部触点数量的系统和方法，而不减少集成电路内部对半导体封装使用的地址，数据和控制信号的数量。在一些实施例中，可以在共享导体处接收两个信号，该共享导体可由半导体封装外部的器件访问，并且传送到集成电路上对半导体封装的外部不可访问的两个触点。在各种实施例中，使用减少数量的外部触点来传送支持JEDEC JESD79E标准或JEDEC JESD79-2C标准的全部特征所需的信号。

5. 发明申请

WO2007032904A3 SHARED BOND PAD FOR TESTING A MEMORY WITHIN A PACKAGED SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2007032904A3
公开(公告)日：2007-03-22
申请号：PCT/US2006/033731
申请日：2006-08-28
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian E.
发明人： ONG, Adrian E.
IPC分类号： G01R31/26
摘要： A system is provided for communicating with a device within a packaged semiconductor device through a shared external terminal thereof. As one example, the system provides for testing a memory within the package. In addition to the device and the shared external terminal, the system includes a command register that receives a plurality of command signals, and digital logic devices coupled between the external terminal and the command register. Each of the digital logic devices receives a different clock signal and outputs one of the command signals to the command register. The command signals are provided to the external terminal in a sequence that is coordinated with the clock signals so that each digital logic device buffers one of the command signals.

6. 发明申请

WO2007024656A2 ARCHITECTURE AND METHOD FOR TESTING OF AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：用于测试集成电路设备的体系结构和方法
公开(公告)号：WO2007024656A2
公开(公告)日：2007-03-01
申请号：PCT/US2006/032268
申请日：2006-08-18
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian E.
发明人： ONG, Adrian E.
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31926 , G01R31/31723 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G01R31/31917
摘要： In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.
摘要翻译：在一个实施例中，本发明提供了一种硬件和/或软件的平台，其使得能够对封装内的多个集成电路（IC）器件进行完全访问和可靠测试。该平台可以包括测试组件（例如，测试电路，测试焊盘，共享焊盘等），一个或多个探针卡和相关硬件，晶圆探测器程序，外部测试设备的负载板和相关硬件以及软件和例程为最终的测试程序。

7. 发明申请

WO2007022446A2 ELECTRONIC DEVICE HAVING AN INTERFACE SUPPORTED TESTING MODE 审中-公开
标题翻译：具有接口支持测试模式的电子设备
公开(公告)号：WO2007022446A2
公开(公告)日：2007-02-22
申请号：PCT/US2006/032416
申请日：2006-08-17
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian
发明人： ONG, Adrian
IPC分类号： G01R31/26
CPC分类号： G01R31/318513 , G01R31/31701 , G01R31/3172 , G01R31/31723 , G01R31/319 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H01L2224/05554 , H01L2224/48139
摘要： A system is provided for testing a first integrated circuit chip associated with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test mode.
摘要翻译：提供了一种用于测试与半导体器件中的至少第二集成电路芯片相关联的第一集成电路芯片的系统，其中半导体器件的至少一些外部端子将由第一和第二集成电路芯片共享，并且其中第一个集成电路芯片设计用于正常操作和测试模式。该系统包括多个多路复用器电路。当第一集成电路芯片处于正常操作时，每个复用器电路可操作以从第二集成电路芯片接收相应的信号。当第一集成电路芯片处于测试模式时，每个复用器电路还可操作以从第二集成电路芯片或相关联的外部端子接收相应的信号。半导体器件的外部端子可操作以接收用于使第一集成电路芯片在正常操作和测试模式之间转变的信号。

8. 发明申请

WO2006101984A2 INTERNALLY GENERATING PATTERNS FOR TESTING IN AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：用于在集成电路设备中测试的内部生成模式
公开(公告)号：WO2006101984A2
公开(公告)日：2006-09-28
申请号：PCT/US2006/009532
申请日：2006-03-16
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian, E.
发明人： ONG, Adrian, E.
IPC分类号： G11C7/00
CPC分类号： G11C29/20 , G01R31/31813 , G11C2029/3602 , H01L24/06 , H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49109 , H01L2224/49175 , H01L2924/01021 , H01L2924/01055 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： In a first integrated circuit chip contained in a single package along with a second integrated circuit chip, a system includes circuitry on the first integrated circuit chip for receiving address signals from the second integrated circuit chip during normal operation. Circuitry on the first integrated circuit chip generates address signals for use in testing the first integrated chip in a test mode.
摘要翻译：在与第二集成电路芯片一起包含在单个封装中的第一集成电路芯片中，系统包括在第一集成电路芯片上的电路，用于在正常操作期间从第二集成电路芯片接收地址信号。第一集成电路芯片上的电路产生用于在测试模式下测试第一集成芯片的地址信号。

9. 发明申请

WO2007024656A9 ARCHITECTURE AND METHOD FOR TESTING OF AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：用于测试集成电路设备的架构和方法
公开(公告)号：WO2007024656A9
公开(公告)日：2007-04-12
申请号：PCT/US2006032268
申请日：2006-08-18
申请人： INAPAC TECHNOLOGY INC , ONG ADRIAN E
发明人： ONG ADRIAN E
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G06F11/00
CPC分类号： G01R31/31926 , G01R31/31723 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G01R31/31917
摘要： In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.
摘要翻译：在一个实施例中，本发明提供了一种硬件和/或软件平台，其能够对封装内的多个集成电路（IC）器件进行完全访问和可靠测试。该平台可以包括测试部件（例如，测试电路，测试焊盘，共享焊盘等），一个或多个探针卡和相关硬件，晶片探针程序，负载板和外部测试设备的相关硬件以及软件和例程用于最终测试程序。

10. 发明申请

WO2007024656A3 ARCHITECTURE AND METHOD FOR TESTING OF AN INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：WO2007024656A3
公开(公告)日：2007-03-01
申请号：PCT/US2006/032268
申请日：2006-08-18
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian E.
发明人： ONG, Adrian E.
IPC分类号： G01R31/28 , G01R27/28
摘要： In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices (20, 30) within a package. This platform may include a testing component (10) (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe program, load board and related hardware of external test equipment, and software and routines for final test programs.

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