专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011119405A2 METHOD AND CIRCUIT FOR TESTING AND CHARACTERIZING HIGH SPEED SIGNALS USING AN ON-CHIP OSCILLOSCOPE 审中-公开
标题翻译：用于测试和表征使用片上振荡器的高速信号的方法和电路
公开(公告)号：WO2011119405A2
公开(公告)日：2011-09-29
申请号：PCT/US2011/028814
申请日：2011-03-17
申请人： MOSYS, INC. , CHOPRA, Rajesh
发明人： CHOPRA, Rajesh
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R13/0272 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/48 , H03K5/133
摘要： A method and structure for characterizing signals used to operate high speed circuitry on an integrated circuit chip. Signals to be characterized, such as column select signals, sense amplifier enable signals and word line signals, are generated on the chip. Each of these signals has an identical corresponding pattern during successive cycles of an input clock signal. These signals are sampled on the chip with successively delayed versions of the input clock signal, thereby generating a plurality of data samples that represent the patterns of the signals over a cycle of the input clock signal. The data samples are stored in a memory block on the chip, and are subsequently serialized and transferred to a location external to the chip.
摘要翻译：用于表征用于在集成电路芯片上操作高速电路的信号的方法和结构。要在芯片上产生要表征的信号，如列选择信号，读出放大器使能信号和字线信号。这些信号中的每一个在输入时钟信号的连续周期期间具有相同的对应模式。这些信号在芯片上采用连续延迟版本的输入时钟信号进行采样，从而在输入时钟信号的周期上产生表示信号模式的多个数据样本。数据样本存储在芯片上的存储器块中，随后被串行化并传送到芯片外部的位置。

2. 发明申请

WO2009126812A1 PROGRAMMABLE MEMORY REPAIR SCHEME 审中-公开
标题翻译：可编程存储器维修方案
公开(公告)号：WO2009126812A1
公开(公告)日：2009-10-15
申请号：PCT/US2009/040079
申请日：2009-04-09
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian, E. , HO, Fan
发明人： ONG, Adrian, E. , HO, Fan
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G11C11/401 , G11C11/4085 , G11C29/027 , G11C29/04 , G11C29/12 , G11C29/4401 , G11C29/48 , G11C29/78 , G11C29/789 , G11C29/802 , G11C2229/743
摘要： The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.
摘要翻译：本公开提供了用于测试和操作该半导体器件的方法，系统和装置。半导体存储器件包括数据存储元件和修复电路。数据存储元件包括主数据存储元件和一个或多个冗余数据存储元件，主数据存储元件具有用于存储器存取操作的相应地址。修复电路由与存储器件分开的另一个半导体器件可编程，以识别主数据存储元件的故障地址，并且编程的修复电路被配置为将存储器访问从具有识别的故障地址的主数据存储元件重新路由到相应的冗余数据存储元件。

3. 发明申请

WO2007023458A2 CONTROLLING EMBEDDED MEMORY ACCESS 审中-公开
标题翻译：控制嵌入式存储器访问
公开(公告)号：WO2007023458A2
公开(公告)日：2007-03-01
申请号：PCT/IB2006/052906
申请日：2006-08-22
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KHANH, Ata , GOODHUE, Greg , SHRIVASTAVA, Pankaj
发明人： KHANH, Ata , GOODHUE, Greg , SHRIVASTAVA, Pankaj
IPC分类号： G06F21/02 , G01R31/317
CPC分类号： G01R31/31719 , G01R31/318533 , G06F21/74 , G11C29/48 , G11C2029/0401 , G11C2029/5602
摘要： A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.
摘要翻译：微控制器（30）包括处理器（32），可操作地耦合到处理器（32）的嵌入式存储器（46）以及可操作地连接到处理器（32）的微控制器测试接口）和存储器（36）。微控制器（30）响应复位信号以执行复位启动，该复位启动导致测试接口（34）的初始禁用状态被设置并且与处理器（32）一起执行启动代码。该代码执行可选地建立进一步的禁用状态。微控制器（30）在复位启动之后的微控制器（30）操作期间通过测试接口（34）提供用于存储器（46）访问的测试接口的启用状态，除非进一步禁用的存储器执行启动代码。

4. 发明申请

WO2007022446A2 ELECTRONIC DEVICE HAVING AN INTERFACE SUPPORTED TESTING MODE 审中-公开
标题翻译：具有接口支持测试模式的电子设备
公开(公告)号：WO2007022446A2
公开(公告)日：2007-02-22
申请号：PCT/US2006/032416
申请日：2006-08-17
申请人： INAPAC TECHNOLOGY, INC. , ONG, Adrian
发明人： ONG, Adrian
IPC分类号： G01R31/26
CPC分类号： G01R31/318513 , G01R31/31701 , G01R31/3172 , G01R31/31723 , G01R31/319 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H01L2224/05554 , H01L2224/48139
摘要： A system is provided for testing a first integrated circuit chip associated with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test mode.
摘要翻译：提供了一种用于测试与半导体器件中的至少第二集成电路芯片相关联的第一集成电路芯片的系统，其中半导体器件的至少一些外部端子将由第一和第二集成电路芯片共享，并且其中第一个集成电路芯片设计用于正常操作和测试模式。该系统包括多个多路复用器电路。当第一集成电路芯片处于正常操作时，每个复用器电路可操作以从第二集成电路芯片接收相应的信号。当第一集成电路芯片处于测试模式时，每个复用器电路还可操作以从第二集成电路芯片或相关联的外部端子接收相应的信号。半导体器件的外部端子可操作以接收用于使第一集成电路芯片在正常操作和测试模式之间转变的信号。

5. 发明申请

WO2005043276A2 SYSTEM-IN-PACKAGE AND METHOD OF TESTING THEREOF 审中-公开
标题翻译：系统级封装及其测试方法
公开(公告)号：WO2005043276A2
公开(公告)日：2005-05-12
申请号：PCT/IL2004/000941
申请日：2004-10-13
申请人： M-SYSTEMS FLASH DISK PIONEERS LTD. , AVRAHAM, Meir
发明人： AVRAHAM, Meir
IPC分类号： G06F
CPC分类号： G11C29/48 , G01R31/318513 , G11C29/1201 , G11C2029/0401 , G11C2029/1208
摘要： A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.
摘要翻译：一种测试具有CPU，非易失性存储器和易失性存储器的SIP的方法。首先，CPU用于测试记忆。然后分别测试CPU。优选地，用于测试存储器的程序预先存储在非易失性存储器中并从非易失性存储器加载到易失性存储器中，并且由易失性存储器中的CPU执行。优选地，将测试结果存储在非易失性存储器中。

6. 发明申请

WO2005026966A1 レジスタファイル及びその記憶素子审中-公开
标题翻译：注册文件及其存储元素
公开(公告)号：WO2005026966A1
公开(公告)日：2005-03-24
申请号：PCT/JP2003/011410
申请日：2003-09-08
申请人：富士通株式会社 , 田中智浩
发明人：田中智浩
IPC分类号： G06F12/16
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318552 , G11C29/48 , G11C2029/3202
摘要： A scan control circuit sends the first shift clock to a scan connection configuration circuit and to a memory array from the last register to the first register sequentially. By doing so, data is first copied in parallel from the first element of the last register of the memory array to the second storage element of the scan connection configuration circuit, and shift data is output externally from the second storage element of the least-significant bit of the scan connection configuration circuit to the shift register output terminal. Next, data is sequentially copied in parallel from the first storage elements of a high-order register in the memory array to the first storage elements of a low-order register. For the first register, data in the second storage elements except the most-significant bit of the scan connection configuration circuit is copied in parallel to the first storage elements except the most-significant bit. Last, shift data received externally at the shift register input terminal is copied by inputting a second shift clock into the first storage element of the most-significant bit of the first register. This processing is repeated until all data held in the memory array at scan start time is output externally from the shift register output terminal.
摘要翻译：扫描控制电路将扫描连接配置电路和从最后一个寄存器到第一寄存器的存储器阵列顺序地发送第一移位时钟。通过这样做，数据首先从存储器阵列的最后一个寄存器的第一个元件并行复制到扫描连接配置电路的第二个存储元件，并且移位数据从最不重要的第二个存储元件向外部输出扫描连接配置电路的位到移位寄存器输出端子。接下来，将数据从存储器阵列中的高位寄存器的第一存储元件并行顺序复制到低位寄存器的第一存储元件。对于第一寄存器，除了扫描连接配置电路的最高有效位之外的第二存储元件中的数据与除最高有效位之外的第一存储元件并行复制。最后，通过将第二移位时钟输入到第一寄存器的最高有效位的第一存储元件来复制在移位寄存器输入端从外部接收的移位数据。重复该处理，直到在扫描开始时刻保存在存储器阵列中的所有数据从移位寄存器输出端子外部输出。

7. 发明申请

WO2004001568A3 SINGLE PIN MULTILEVEL INTEGRATED CIRCUIT TEST INTERFACE 审中-公开
标题翻译：单引脚多路集成电路测试接口
公开(公告)号：WO2004001568A3
公开(公告)日：2004-03-18
申请号：PCT/IB0302380
申请日：2003-06-19
申请人： MELEXIS NV , DE WINTER RUDI
发明人： DE WINTER RUDI
IPC分类号： G01R31/317 , G01R31/3185 , G11C7/10 , G11C29/48 , H03K19/173
CPC分类号： G11C29/1201 , G01R31/31701 , G01R31/318572 , G11C7/1078 , G11C7/109 , G11C29/48 , H03K19/1732
摘要： An integrated circuit (102) comprises one or more integrated circuit elements which may interact with other circuitry via one or more input/output pins. In the present invention the circuit elements include and interface element (101) for interfacing with external test circuitry. The interface element communicates with the external test circuitry via a single input/output pin (201) dedicated for testing.
摘要翻译：集成电路（102）包括一个或多个集成电路元件，其可以经由一个或多个输入/输出引脚与其它电路相互作用。在本发明中，电路元件包括用于与外部测试电路接口的接口元件（101）。接口元件通过专用于测试的单个输入/输出引脚（201）与外部测试电路通信。

8. 发明申请

WO0195117A3 DATA PROCESSING SYSTEM FOR HIGH SPEED MEMORY TEST 审中-公开
标题翻译：高速记忆测试数据处理系统
公开(公告)号：WO0195117A3
公开(公告)日：2002-08-08
申请号：PCT/RU0100234
申请日：2001-06-06
申请人： ABROSIMOV IGOR ANATOLIEVICH , KLOTCHKOV ILYA VALERIEVICH
发明人： ABROSIMOV IGOR ANATOLIEVICH , KLOTCHKOV ILYA VALERIEVICH
IPC分类号： G11C29/48 , G11C29/56 , G11C29/00
CPC分类号： G11C29/56012 , G11C29/48 , G11C29/56 , G11C2029/5602
摘要： The present invention relates generally to data processing systems, in particular, to computer-controlled automatic test systems for testing integrated circuits, and more particularly to memory test systems which interface with high speed protocol memories such as synchronous DRAM, in particular DDR.A data processing system comprises a data transmitter having a plurality of data transmitting sections operable in parallel for transmitting data, wherein the data trasmitter additionally comprises a circuit for synchronising said parallel data transmitting sections; a programmable frequency clock generator for generating a clock signal, wherein said programmed frequency includes a full-frequency and a low-frequency, the low frequency being a quotient of the full frequency and a number of said data transmitting sections; a multiplexer that receives data from said data transmitting sections at said low frequency and provides multiplexed output data at said full frequency; a plurality of registers for latching data and supplying latched data to a plurality of logic devices; wherein said data transmitting sections, said registers and said receiving devices operate at said low frequency; while said output data are transmitted and received at said full frequency.
摘要翻译：本发明一般涉及数据处理系统，特别涉及用于测试集成电路的计算机控制的自动测试系统，更具体地涉及与诸如同步DRAM（特别是DDR）的高速协议存储器接口的存储器测试系统.A数据处理系统包括数据发送器，具有可并行操作以发送数据的多个数据发送部分，其中所述数据传送器还包括用于同步所述并行数据发送部分的电路; 用于产生时钟信号的可编程频率时钟发生器，其中所述编程频率包括全频率和低频率，所述低频率是所述全频率的商和所述数据发送部分的数量; 多路复用器，以所述低频率从所述数据发送部分接收数据，并以所述全频率提供复用的输出数据; 多个寄存器，用于锁存数据并将锁存数据提供给多个逻辑器件; 其中所述数据发送部分，所述寄存器和所述接收装置以所述低频工作; 而所述输出数据以所述全频率发送和接收。

9. 发明申请

WO01050474A1 METHOD AND APPARATUS FOR EXERCISING EXTERNAL MEMORY WITH A MEMORY BUILT-IN SELF-TEST 审中-公开
标题翻译：用记忆体内置自检来锻炼外部存储器的方法和装置
公开(公告)号：WO01050474A1
公开(公告)日：2001-07-12
申请号：PCT/US2000/015476
申请日：2000-06-05
IPC分类号： G01R31/28 , G06F11/22 , G06F12/16 , G11C29/48 , G11C29/56 , G11C29/00 , H04L12/26
CPC分类号： G06F11/2289 , G11C29/48
摘要： A method and arrangement for testing external memories of different types coupled to a network interface controller interprets the results of the memory test differently in accordance with the memory test differently in accordance with the memory type. A fail state indicator is used by test controller to indicate the proper offset to add or subtract to a test address to calculate the actual failing memory location.
摘要翻译：用于测试耦合到网络接口控制器的不同类型的外部存储器的方法和装置根据存储器类型不同地根据存储器测试不同地解释存储器测试的结果。测试控制器使用故障状态指示器来指示适当的偏移量，以对测试地址进行加法或减法，以计算实际的故障存储器位置。

10. 发明申请

WO00073809A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：WO00073809A1
公开(公告)日：2000-12-07
申请号：PCT/JP1999/002755
申请日：1999-05-26
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/318558 , G01R31/318541 , G01R31/318555 , G01R31/318572 , G06F11/2236 , G11C29/48 , G11C2029/3202
摘要： A semiconductor integrated circuit which is provided with a shift scan path incorporated in each function module and a testing I/O terminal connected to a shift scan path and provided separately from a normal-operation-use I/O terminal, and which comprises, all formed on one semiconductor chip, a bus interface circuit for connecting normal-operation-use I/O terminals of a plurality of function modules to a bus, an external interface switching circuit which switches between the bus-side I/O terminal of the bus interface circuit and the testing I/O terminal of each function module for connection to an external terminal and an interface control circuit for switch-controlling the external interface switching circuit.
摘要翻译：一种半导体集成电路，其具有并入每个功能模块中的移位扫描路径和连接到移位扫描路径并与常规操作用I / O端子分开设置的测试I / O端子，并且包括全部形成在一个半导体芯片上，用于将多个功能模块的正常操作用I / O端子连接到总线的总线接口电路，在总线的总线侧I / O端子之间切换的外部接口切换电路接口电路和用于连接到外部端子的每个功能模块的测试I / O端子和用于开关控制外部接口切换电路的接口控制电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式