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1. 发明申请

WO2005088644A1 DFT TECHNIQUE FOR STRESSING SELF-TIMED SEMICONDUCTOR MEMORIES TO DETECT DELAY FAULTS 审中-公开
标题翻译：用于压制自身半导体存储器的DFT技术来检测延迟故障
公开(公告)号：WO2005088644A1
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050800
申请日：2005-03-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , U.S. PHILIPS CORPORATION , AZIMANE, Mohamed , MAJHI, Ananta
发明人： AZIMANE, Mohamed , MAJHI, Ananta
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/024 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C29/56012
摘要： The present invention relates to a test system (100) interposed between a clock monitor (152) and an internal memory block (125) of a self-timed memory. In an example embodiment, the test system (100) receives an internal clock signal (104) from the clock monitor (152), an external clock signal (CL) and a control signal (CS). A multiplexer (110) of the test system provides in dependence upon the control signal (CS) the internal clock signal (104) to the internal memory block (125) during a normal mode of operation of the self-timed memory and the external clock signal (CL) to the internal memory block (125) during a test mode (108) of the self-timed memory. The test system (100) enables control of the clock cycle of the internal memory block (125) by directly applying the external clock signal (CL) during test mode. Thus, the internal memory block is stressed properly enabling the detection of small delay faults.
摘要翻译：本发明涉及一种插入在自定时存储器的时钟监视器（152）和内部存储块（125）之间的测试系统（100）。在示例性实施例中，测试系统（100）从时钟监视器（152），外部时钟信号（CL）和控制信号（CS）接收内部时钟信号（104）。在自定时存储器和外部时钟的正常操作模式期间，测试系统的多路复用器（110）根据控制信号（CS）提供内部存储器块（125）的内部时钟信号（104）在自定时存储器的测试模式（108）期间向内部存储器块（125）发送信号（CL）。测试系统（100）通过在测试模式期间直接施加外部时钟信号（CL）来实现内部存储器块（125）的时钟周期的控制。因此，内部存储器块被适当地压缩，能够检测到小的延迟故障。

2. 发明申请

WO2005088643A1 METHOD FOR DETECTING RESISTIVE BRIDGE DEFECTS IN THE GLOBAL DATA BUS OF SEMICONDUCTOR MEMORIES 审中-公开
标题翻译：在半导体存储器的全局数据总线中检测电阻桥缺陷的方法
公开(公告)号：WO2005088643A1
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050778
申请日：2005-03-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , AZIMANE, Mohamed , MAJHI, Ananta
发明人： AZIMANE, Mohamed , MAJHI, Ananta
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025
摘要： There is a method (300) for detecting resistive bridge defects in the global data bus (GDB) of a semiconductor memory having N Z-blocks. In an example embodiment, a plurality of data sets (310) with a predetermined test pattern is provided. The plurality of data sets is used to perform (320) write and read operations to at least a predetermined memory position within a Z-block of the N Z-blocks such that each data set is applied to each of the at least a predetermined memory position. To sensitize weak bridge defects (105), the write and read operations of the same data sets to the same memory locations are repeated. (330) consecutively for at least four times. These steps are repeated for all Zblocks of the memory. Resistive bridge defects are detected in the GDB of the memory in a way that covers substantially all possible locations for bridge defects (105) as well as weak bridge defects, while substantially reducing test complexity and time.
摘要翻译：存在用于检测具有N个Z块的半导体存储器的全局数据总线（GDB）中的电阻性电桥缺陷的方法（300）。在示例性实施例中，提供具有预定测试图案的多个数据集（310）。多个数据组用于对N个Z块的Z块内的至少预定的存储位置执行（320）写入和读取操作，使得每个数据组被应用于至少一个预定存储器位置。为了使弱桥缺陷（105）敏感，重复将相同数据集写入和读操作相同的存储器位置。（330）连续至少四次。对于内存的所有Zblock重复这些步骤。电阻桥缺陷在存储器的GDB中以覆盖桥接缺陷（105）的基本上所有可能的位置以及弱桥接缺陷的方式被检测到，同时大大降低了测试的复杂性和时间。

3. 发明申请

WO2004105043A1 TESTING RAM ADDRESS DECODER FOR RESISTIVE OPEN DEFECTS 审中-公开
标题翻译：测试电阻开路缺陷的RAM地址解码器
公开(公告)号：WO2004105043A1
公开(公告)日：2004-12-02
申请号：PCT/IB2004/050696
申请日：2004-05-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AZIMANE, Mohamed , MAJHI, Ananta, K.
发明人： AZIMANE, Mohamed , MAJHI, Ananta, K.
IPC分类号： G11C29/00
CPC分类号： G11C29/02
摘要： Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types of faults is proposed, in which two cells of two logically adjacent rows or columns are written with complementary logic data. If a read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect is demonstrated. The read and write operations each occur as a result of a clock pulse, and the method includes the steps of setting a clock cycle such that, in the event that said first cell is demonstrating slow-to-fall behavior, the reading cycle will be caused to be performed before the logic state of said first cell has fallen to its minimum level, and/or of setting the width of said clock pulses such that, in the event that the first cell is demonstrating slow-to-rise behavior, the reading cycle will be caused to be performed before the logic state of said first cell has risen to its maximum level.
摘要翻译：例如地址解码器和导致逻辑和顺序延迟行为的电压源的逻辑门之间的硬开放缺陷使得存储器在条件上不起作用。提出了一种用于测试这些类型故障的集成电路的方法和装置，其中两个逻辑相邻的行或列的两个单元被写入互补逻辑数据。如果读取操作显示两个单元格中的数据相同，则会显示硬开放缺陷的存在和位置。读取和写入操作各自作为时钟脉冲的结果而发生，并且该方法包括设置时钟周期的步骤，使得在所述第一小区示出缓慢到下降的行为的情况下，读取周期将是导致在所述第一单元的逻辑状态已经下降到其最小电平之前执行，和/或设置所述时钟脉冲的宽度，使得在第一单元显示缓慢上升行为的情况下，在所述第一单元的逻辑状态上升到其最大电平之前，将执行读取周期。

4. 发明申请

WO2004105044A1 TESTING INTEGRATED CIRCUITS 审中-公开
标题翻译：测试集成电路
公开(公告)号：WO2004105044A1
公开(公告)日：2004-12-02
申请号：PCT/IB2004/050698
申请日：2004-05-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AZIMANE, Mohamed , MAJHI, Ananta, Kumar
发明人： AZIMANE, Mohamed , MAJHI, Ananta, Kumar
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/54
摘要： A method and apparatus for diagnosing resistive open defects in address decoders and, in particular memory address decoders. The method and apparatus accelerate the diagnosis process of detecting any resistive open defects that may occur during production, particularly where time-to market is a very important factor. Based on the disclosed invention, many actions for improving yield can be taken. In accordance with the invention, there is created a fault dictionary of resistive-open defects based on defect location, transistor types, terminal names and also the fault behavior. The dictionary enhances the diagnosing capabilities and also helps in differentiating between resistive bridge and resistive open defects.
摘要翻译：一种用于诊断地址解码器中的电阻性开路缺陷的方法和装置，特别是存储器地址解码器。该方法和设备加速了在生产过程中可能发生的任何电阻性开放缺陷的检测过程，特别是上市时间是非常重要的因素。基于所公开的发明，可以采取许多用于提高产量的动作。根据本发明，基于缺陷位置，晶体管类型，终端名称以及故障行为产生了电阻开路缺陷的故障字典。该字典增强了诊断能力，也有助于区分电阻桥和电阻开路缺陷。

5. 发明申请

WO2005093761A1 METHOD FOR DETECTING RESISTIVE-OPEN DEFECTS IN SEMICONDUCTOR MEMORIES 审中-公开
标题翻译：用于检测半导体存储器中电阻开路缺陷的方法
公开(公告)号：WO2005093761A1
公开(公告)日：2005-10-06
申请号：PCT/IB2005/051006
申请日：2005-03-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , U.S. PHILIPS CORPORATION , AZIMANE, Mohamed
发明人： AZIMANE, Mohamed
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50 , G11C29/50008 , G11C29/50012 , G11C29/56004
摘要： The present invention relates to a method for detecting delay faults in a semiconductor memory. In an example embodiment (100), address bits and data bits are generated (110) according to a test pattern suitable for testing the semiconductor memory. The address bits and the data bits are validated (120) and then provided to input ports (130) of the semiconductor memory. Memory operation (140, 150, 160, 170) is then started such that a time interval between the provision of the address bits and the data bits and the start of the memory operation is approximately equal to an operating clock cycle of the semiconductor memory. Such timing ensures that both the address decoder and the read/write circuitry are stressed in time appropriately, enabling detection of small delay faults.
摘要翻译：本发明涉及一种用于检测半导体存储器中的延迟故障的方法。在示例性实施例（100）中，根据适合于测试半导体存储器的测试模式来生成地址位和数据位（110）。地址位和数据位被验证（120），然后提供给半导体存储器的输入端口（130）。然后开始存储器操作（140,150,160,170），使得提供地址位和数据位之间的时间间隔和存储器操作的开始大约等于半导体存储器的工作时钟周期。这种定时确保地址解码器和读/写电路在时间上适当地受到应力，从而能够检测到小的延迟故障。

6. 发明申请

WO2006056902A1 SRAM TEST METHOD AND SRAM TEST ARRANGEMENT TO DETECT WEAK CELLS 审中-公开
标题翻译： SRAM测试方法和SRAM测试安排以检测弱电池
公开(公告)号：WO2006056902A1
公开(公告)日：2006-06-01
申请号：PCT/IB2005/053677
申请日：2005-11-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PINEDA DE GYVEZ, Jose de Jesus , AZIMANE, Mohamed , PAVLOV, Andrei, S.
发明人： PINEDA DE GYVEZ, Jose de Jesus , AZIMANE, Mohamed , PAVLOV, Andrei, S.
IPC分类号： G11C29/50
CPC分类号： G11C29/50
摘要： A method and a test arrangement for testing an SRAM having a first cell and a second cell coupled between a pair of bitlines is disclosed. In a first step (410), a data value is stored in the first cell being the cell under test (CUT), and its complement is stored in a second cell, being the reference cell. Next, the bitlines are precharged to a predefined voltage (step 420). Subsequently, the wordline of the reference cell is enabled for a predefined time period (step 430), for instance by providing the wordline with a number of voltage pulses. This causes a drop in voltage of the bitline coupled to the logic '0' node of the reference cell. In a subsequent step (440), the wordline of the CUT is enabled, which exposes the CUT to the bitline with the reduced voltage. This is equivalent to weakly overwriting the CUT. Finally, the data value in the CUT is evaluated. If the data value has flipped, the CUT is a weak cell. Cells with varying levels of weakness can be detected by varying the reduced voltage on the aforementioned bitline.
摘要翻译：公开了一种用于测试具有耦合在一对位线之间的第一单元和第二单元的SRAM的方法和测试装置。在第一步骤（410）中，数据值存储在作为被测单元（CUT）的第一单元中，并且其补码存储在作为参考单元的第二单元中。接下来，将位线预充电到预定电压（步骤420）。随后，参考单元的字线被启用预定时间段（步骤430），例如通过为字线提供多个电压脉冲。这导致耦合到参考单元的逻辑“0”节点的位线的电压下降。在随后的步骤（440）中，CUT的字线被使能，其将CUT以降低的电压公开到位线。这相当于弱覆盖了CUT。最后，评估CUT中的数据值。如果数据值已翻转，则CUT是弱单元。可以通过改变上述位线上的降低的电压来检测具有不同弱度水平的细胞。

7. 发明申请

WO2004105045A1 TEST OF RAM ADDRESS DECODER FOR RESISTIVE OPEN DEFECTS 审中-公开
标题翻译：用于电阻开路缺陷的RAM地址解码器的测试
公开(公告)号：WO2004105045A1
公开(公告)日：2004-12-02
申请号：PCT/IB2004/050708
申请日：2004-05-17
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AZIMANE, Mohamed
发明人： AZIMANE, Mohamed
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/10
摘要： A new test pattern which consists of performing "very small jumps" and "very big jumps" within the matrix. The "very small jumps" are controlled by the row decoder, and have the effect of sensitizing the resistive open defects which lead to slow-to-fall behavior in the word line. A "very small jump" means that the memory position of two consecutive accesses remains in a unique sub-cluster until all rows in that sub-cluster have been tested, remains in the same cluster until all rows in that cluster have been tested, remains in the same U section until all rows in that U section have been tested, and finally, remains in the same Z block until all of the rows of that Z block have been tested. The "very big jumps" are intended to cover the class of resistive open defects which leads to slow-to-rise behavior, and is intended to mean that two consecutive memory accesses must never stay in the same subcluster, at the same cluster, or at the same U section.
摘要翻译：一种新的测试模式，其中包括在矩阵内执行“非常小的跳跃”和“非常大的跳跃”。 “非常小的跳跃”由行解码器控制，并且具有使电阻性开放缺陷敏感的效果，这导致字线中的缓慢下降行为。 “非常小的跳转”意味着两个连续访问的内存位置保留在唯一的子集群中，直到该子集群中的所有行都已经过测试，保持在相同的集群中，直到该集群中的所有行都被测试为止在相同的U部分中，直到该U部分中的所有行已经过测试，最后，保持在相同的Z块中，直到该Z块的所有行已经过测试。 “非常大的跳跃”旨在涵盖导致缓慢上升行为的电阻性开放缺陷的类别，意在意味着两个连续的存储器访问不能停留在相同的子集群中，在相同的集群处，或者在同一个U部分。

8. 发明申请

WO2008023334A2 METHOD FOR TESTING A STATIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：测试静态随机存取存储器的方法
公开(公告)号：WO2008023334A2
公开(公告)日：2008-02-28
申请号：PCT/IB2007/053337
申请日：2007-08-21
申请人： NXP B.V. , WIELAGE, Paul , AZIMANE, Mohamed
发明人： WIELAGE, Paul , AZIMANE, Mohamed
IPC分类号： G11C29/50
CPC分类号： G11C29/50 , G11C11/41
摘要： A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word line (WL) coupled to the memory cell under test is activated for a predetermined period. During a first part of this period, one of the bit lines (BLB) is kept at the low potential to force the associated pull up transistor in the CUT into a conductive state, after which this bit line (BLB) is charged to a high potential. Upon completion of this period, the bit value of the first cell is determined. The method facilitates the detection of weak or faulty SRAM cells without requiring the inclusion of dedicated hardware for this purpose.
摘要翻译：公开了一种测试具有多个存储器单元的SRAM的方法。第一步，将一个位值写入被测试单元（CUT）。随后，第一和第二使能晶体管被禁止，并且位线被放电到低电位。接下来，耦合到被测试存储器单元的字线（WL）被激活预定时间段。在此期间的第一部分期间，位线（BLB）中的一条保持在低电位以迫使CUT中的相关联的上拉晶体管进入导通状态，此后，该位线（BLB）被充电至高电位潜在。在完成这段时间后，确定第一个单元的比特值。该方法有助于检测弱或有故障的SRAM单元，而无需为此目的包含专用硬件。

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