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51. 发明申请

WO2016053557A1 ALTERNATING REFRACTIVE INDEX IN CHARGE-TRAPPING FILM IN THREE-DIMENSIONAL MEMORY 审中-公开
标题翻译：三维存储器中电荷捕捉膜中的替代折射率
公开(公告)号：WO2016053557A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/048000
申请日：2015-09-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： PANG, Liang , DONG, Yingda , PACHAMUTHU, Jayavel
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/1052 , H01L27/1157 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： Techniques for fabricating a three-dimensional, charge-trapping memory device with improved long term data retention, and a corresponding three-dimensional, charge-trapping memory device including a stack of alternating word line layers and dielectric layers. A charge-trapping layer is deposited in a memory hole. The refractive index of portions of the charge-trapping layer adjacent to the word line layers is increased relative to the refractive index of portions of the charge-trapping layer which are adjacent to the dielectric layers. This can be achieved by doping the portions of the charge-trapping layer adjacent to the word line layers. In one approach, the charge-trapping layer is SiON doped with Si or N. In another approach, the charge-trapping layer is HfO doped with Hf. In another approach, the charge-trapping layer is HfSiON doped with Hf, Si or N.
摘要翻译：用于制造具有改进的长期数据保留的三维电荷捕获存储器件以及相应的三维电荷捕获存储器件的技术，其包括交替的字线层和电介质层的堆叠。电荷捕获层沉积在存储器孔中。与字线层相邻的电荷俘获层的部分的折射率相对于与电介质层相邻的电荷俘获层的部分的折射率增加。这可以通过掺杂与字线层相邻的电荷俘获层的部分来实现。在一种方法中，电荷捕获层是掺杂有Si或N的SiON。在另一种方法中，电荷俘获层是掺杂有Hf的HfO。在另一种方法中，电荷俘获层是掺杂有Hf，Si或N的HfSiON。

52. 发明申请

WO2016039975A1 CONTROLLING PASS VOLTAGES TO MINIMIZE PROGRAM DISTURB IN CHARGE-TRAPPING MEMORY 审中-公开
标题翻译：控制电源电压以最小化充电跟踪存储器中的程序干扰
公开(公告)号：WO2016039975A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/046679
申请日：2015-08-25
申请人： SANDISK TECHNOLOGIES INC.
发明人： DONG, Yingda , CHEN, Hong-Yan
IPC分类号： G11C16/34 , G11C11/56 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459
摘要： Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.
摘要翻译：提供技术用于防止在包括二维或三维配置的连续电荷俘获层的NAND串中的所选存储单元的编程期间防止未选择存储单元的程序干扰。在这种NAND串中，由于程序电压和字线上的通过电压，存储单元之间的区域可能被无意地编程为寄生单元。对于编程单元，通过在相邻的后面编程的字线上提供比在相邻的预先编程的字线上更高的通过电压，可以避免由寄生电池引起的阈值电压升档。对于已擦除的单元，可以通过逐渐降低相邻的后编程字线上的通过电压来降低由寄生电池引起的阈值电压升档。当最低目标数据状态的存储单元完成编程时，可能会发生降低。

53. 发明申请

WO2016022321A1 ADAPTIVE SELECTIVE BIT LINE PRE-CHARGE FOR CURRENT SAVINGS AND FAST PROGRAMMING 审中-公开
标题翻译：自适应选择位线预付电流节省和快速编程
公开(公告)号：WO2016022321A1
公开(公告)日：2016-02-11
申请号：PCT/US2015/042309
申请日：2015-07-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： MUI, Man L , KOH, Yee Lih , LI, Yenlung , HSU, Cynthia
IPC分类号： G11C11/56 , G11C16/10 , G11C16/24 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C2211/5621
摘要： Techniques are provided for efficiently performing programming operations in a memory device. In particular, power consumption is reduced in sensing circuitry by avoiding pre-charging of bit lines for certain memory cells at certain times. One approach uses knowledge of the different phases of a programming operation to reduce the number of unnecessary bit line pre-charges. For example, during the lower program loop numbers of a programming operation, bit line pre-charging occurs for lower data states but not for higher data states. Similarly, during the higher program loop numbers, bit line pre-charging occurs for higher data states but not for lower data states. In another approach, which may or may not incorporate knowledge of the different phases of a programming operation, the setting of the bit line pre-charge is updated at least once after it is initially set in the verify portion.
摘要翻译：提供了用于在存储器件中有效执行编程操作的技术。特别地，通过避免某些存储器单元的某些位的位线的预充电，感测电路的功耗降低。一种方法使用编程操作的不同阶段的知识来减少不必要的位线预充电的数量。例如，在编程操作的较低程序循环次数期间，针对较低的数据状态发生位线预充电，而对于较高的数据状态而言不发生位线预充电。类似地，在更高的程序循环数期间，对于更高的数据状态而言，位线预充电发生，而对于更低的数据状态则不发生位线预充电。在另一种可能或可能不包含编程操作的不同阶段的知识的方法中，位线预充电的设置在其最初设置在验证部分中之后至少更新一次。

54. 发明申请

WO2015179537A1 INTRINSIC VERTICAL BIT LINE ARCHITECTURE 审中-公开
标题翻译：内部垂直位线架构
公开(公告)号：WO2015179537A1
公开(公告)日：2015-11-26
申请号：PCT/US2015/031804
申请日：2015-05-20
申请人： SANDISK 3D LLC
发明人： RATNAM, Perumal , PETTI, Christopher , YAN, Tianhong
IPC分类号： G11C7/18 , G11C13/00 , H01L27/24
CPC分类号： G11C13/0026 , G11C7/18 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

55. 发明申请

WO2015134632A1 METAL REPLACEMENT PROCESS FOR LOW RESISTANCE SOURCE CONTACTS IN 3D NAND 审中-公开
标题翻译：金属替代流程中的低电阻源联系在3D NAND
公开(公告)号：WO2015134632A1
公开(公告)日：2015-09-11
申请号：PCT/US2015/018774
申请日：2015-03-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： BAENNINGER, Matthias , ALSMEIER, Johann , MATSUDAIRA, Akira , PACHAMUTHU, Jayavel
IPC分类号： H01L27/115
CPC分类号： H01L21/28282 , H01L21/02587 , H01L21/2251 , H01L21/306 , H01L21/31111 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/66666 , H01L29/66833
摘要： A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.
摘要翻译：为3D堆叠的非易失性存储器件提供制造工艺，其提供源极接触到堆叠底部的存储器孔。堆叠包括在衬底上的交替的控制栅极层和介电层，并且通过堆叠蚀刻存储器孔。该过程避免了在存储器孔的底部蚀刻通过膜的需要。相反，从存储孔的底部到堆叠的顶部形成路径。路径包括使用衬底电介质中的空隙沟槽的水平部分和在堆叠中蚀刻的通道。记忆膜，通道材料和电介质材料同时沉积在空隙和存储孔的整个内表面中。该路径被填充金属以形成连续的低电阻导电路径。

56. 发明申请

WO2015053919A1 BIT LINE AND COMPARE VOLTAGE MODULATION FOR SENSING NONVOLATILE STORAGE ELEMENTS 审中-公开
标题翻译：位线和比较电压调制非感觉非易失性存储元件
公开(公告)号：WO2015053919A1
公开(公告)日：2015-04-16
申请号：PCT/US2014/056403
申请日：2014-09-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUNGA, Mohan V. , HIGASHITANI, Masaaki
IPC分类号： G11C16/34 , G11C16/26 , G11C11/56 , G11C5/14 , G11C16/24 , G11C7/12
CPC分类号： G11C16/3454 , G11C7/12 , G11C11/5628 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.
摘要翻译：在一块非易失性存储器中，位线电流随着位线电压而增加。对于电流感测存储器系统，感测操作期间的平均位线电流仅需要超过特定的阈值量以产生正确的结果。对于在块中被编程的第一字线，与其连接的存储器单元在验证操作期间看到相对较低的位线电阻。在所公开的技术中，针对具有较低验证位线电压的这些第一经编程字线执行验证操作，以便减少过量位线电流且节省功率。在读操作期间，该方案可以使连接到较低字线的存储单元的阈值电压看起来较低。为了弥补这种影响，公开了各种方案。

57. 发明申请

WO2015002901A1 DETECTING PROGRAMMED WORD LINES BASED ON NAND STRING CURRENT 审中-公开
标题翻译：基于NAND STRING电流检测编程的字线
公开(公告)号：WO2015002901A1
公开(公告)日：2015-01-08
申请号：PCT/US2014/044953
申请日：2014-06-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： MUI, Man, L. , DONG, Yingda , AVILA, Chirs
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5635 , G11C11/5642 , G11C13/004 , G11C16/26 , G11C16/344 , G11C16/3454
摘要： A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.
摘要翻译：通过在所有存储单元处于导通状态时测量块中的参考组合电流（Iref）来确定NAND串块中的编程字线的数量（Nwl）。随后，为了确定字线是否是编程字线，块中的附加组合电流（Iadd）是用施加到所选字线的分界电压来测量的。如果Idd小于Iref至少有余量，则所选字线被确定为编程字线。当数字相对较小时，通过使擦除验证测试相对难于通过，当数量相对较大时，Nwl可用于调整擦除操作的擦除验证测试。或者，Nwl可用于标识块中的下一个字线进行编程。

58. 发明申请

WO2014137846A1 DEFECT OR PROGRAM DISTURB DETECTION WITH FULL DATA RECOVERY CAPABILITY 审中-公开
标题翻译：缺陷或程序干扰检测具有完整的数据恢复能力
公开(公告)号：WO2014137846A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/019730
申请日：2014-03-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUTTA, Deepanshu , LEE, Dana , LI, Yan , SHAH, Grishma , MOOGAT, Farookh , HIGASHITANI, Masaaki
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C2211/5621 , G11C2211/5642
摘要： A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.
摘要翻译：用于一组非易失性存储元件的编程操作在程序验证测试通过并且发出程序状态=通过之后确定存储元件是否已经被正确编程。使用可选的一个或多个重建读取操作的逻辑运算，从与存储元件相关联的锁存器组重建写入数据。还执行正常读取操作以获得读取数据。确定读取数据和重建的写入数据之间的一些不匹配，并且基于不匹配的数量确定是否需要重写写入数据。

59. 发明申请

WO2014137653A1 HYBRID NON-VOLATILE MEMORY CELLS FOR SHARED BIT LINE 审中-公开
标题翻译：用于共享位线的混合非易失性记忆细胞
公开(公告)号：WO2014137653A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/018126
申请日：2014-02-25
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUNGA, Mohan V. , HIGASHITANI, Masaaki
IPC分类号： G11C16/04 , G11C7/18 , H01L27/115 , G11C16/24
CPC分类号： G11C16/0425 , G11C7/18 , G11C16/0483 , G11C16/24 , H01L27/11524 , H01L27/1157 , H01L29/66825 , H01L29/788
摘要： A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements.
摘要翻译：非易失性存储系统包括多组连接的非易失性存储元件。每个组包括数据非易失性存储元件的公共侧上的多个连接的数据非易失性存储元件和多个选择栅极。多个选择栅极包括第一选择栅极和第二选择栅极。第一选择栅极具有用于组的第一子集的第一阈值电压和由于第二子集的有源区域注入导致第二阈值电压低于第二阈值电压的组的第二子集的第二阈值电压。第一阈值电压。每组的第二选择栅极具有可编程阈值电压。多个位线中的每一个连接到多组连接的非易失性存储元件。

60. 发明申请

WO2014133979A1 DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法
公开(公告)号：WO2014133979A1
公开(公告)日：2014-09-04
申请号：PCT/US2014/018123
申请日：2014-02-25
申请人： SANDISK 3D LLC
发明人： BANDYOPADHYAY, Abhijit , KUMAR, Tanmay , HERNER, Scott Brad , PETTI, Christopher J. , SCHEUERLEIN, Roy E.
IPC分类号： H01L27/102 , G11C17/16 , H01L27/24 , G11C11/56 , H01L45/00 , H01L29/861
CPC分类号： G11C17/165 , G11C11/5692 , G11C17/18 , H01L27/1021 , H01L27/11206 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.
摘要翻译：在一些方面，提供了包括转向元件和存储元件的存储单元。存储元件包括第一导电材料层，设置在第一导电材料层上方的第一介电材料层，设置在第一介电材料层上方的第二导电材料层，设置在第二导电材料层上方的第二介电材料层，以及设置在所述第二介电材料层上方的第三导电材料层。第一导电材料层和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的堆叠。提供了许多其他方面。

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