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1. 发明申请

WO2016031023A1 半導体記憶装置审中-公开
标题翻译：半导体存储设备
公开(公告)号：WO2016031023A1
公开(公告)日：2016-03-03
申请号：PCT/JP2014/072611
申请日：2014-08-28
申请人：株式会社東芝
发明人：駒井　宏充
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26 , G11C7/1051 , G11C7/106 , G11C16/0483 , G11C16/08 , G11C2211/5642 , G11C2211/5647
摘要：　実施形態にかかる半導体記憶装置によれば、複数のデータラッチと、前記複数のデータラッチに共有されるインバータと、を備え、前記インバータは、前記複数のデータラッチを挟む相補のバス間に挿入されている。
摘要翻译：根据本发明的一个实施例的半导体存储装置设置有多个数据锁存器和由多个数据锁存器共享的反相器。反相器插入布置在多个数据锁存器的任一侧的互补总线之间。

2. 发明申请

WO2014107335A1 EXPLOITING PCM WRITE ASYMMETRIES TO ACCELERATE WRITE 审中-公开
标题翻译：开发PCM写入不对称以加速写入
公开(公告)号：WO2014107335A1
公开(公告)日：2014-07-10
申请号：PCT/US2013/076913
申请日：2013-12-20
申请人： UNIVERSITY OF MAINE SYSTEM BOARD OF TRUSTEES
发明人： ZHU, Yifeng , YUE, Jianhui
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2211/5642 , G11C2211/5647
摘要： To improve the write performance of PCM, the disclosed technology, in certain embodiments, provides a new write scheme, referred to herein as two-stage-write, which leverages the speed and power asymmetries of writing a zero bit and a one bit. Writing a data block to PCM is divided into two separated stages, i.e., write-0 stage and write-1 stage. Without violating power constraints, during the write-0 stage, all zero bits in this data block are written to PCM at an accelerated speed; during the write-1 stage, all one bits are written to PCM, with more bits being written concurrently. In certain embodiments, the disclosed technology provides a new coding scheme to improve the speed of the write-1 stage by further increasing the number of bits that can be written to PCM in parallel.
摘要翻译：为了提高PCM的写入性能，在某些实施例中，所公开的技术提供了一种新的写入方案，这里称为两级写入，其利用写零位和一位的速度和功率不对称性。将数据块写入PCM被划分为两个分离的阶段，即写入0阶段和写入阶段。没有违反功率限制，在写0阶段，该数据块中的所有零位都以加速的速度写入PCM; 在写-1阶段，所有一个位都写入PCM，同时写入更多位。在某些实施例中，所公开的技术提供了一种新的编码方案，以通过进一步增加可并行写入PCM的比特数来提高写入级的速度。

3. 发明申请

WO2013015960A2 DETERMINING AND TRANSFERRING DATA FROM A MEMORY ARRAY 审中-公开
标题翻译：确定并传输来自存储阵列的数据
公开(公告)号：WO2013015960A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/045510
申请日：2012-07-05
申请人： MICRON TECHNOLOGY, INC. , HENDRICKSON, Nicholas
发明人： HENDRICKSON, Nicholas
IPC分类号： G11C16/34
CPC分类号： G11C16/26 , G11C7/1033 , G11C7/1036 , G11C7/1039 , G11C7/106 , G11C11/5642 , G11C16/0458 , G11C16/0483 , G11C2207/2272 , G11C2211/5642
摘要： Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.
摘要翻译：公开了操作存储器设备的装置和方法。在一种这样的方法中，存储器单元的数据状态的第一部分被确定并从存储器装置转移，同时继续确定相同存储器单元的数据状态的剩余部分。在至少一种方法中，在第一感测阶段期间确定存储器单元的数据状态，并在存储器单元经历附加感测阶段时传输，以确定存储器单元的数据状态的附加部分。

4. 发明申请

WO2004029977A1 HIGHLY COMPACT NON-VOLATILE MEMORY WITH SPACE-EFFICIENT DATA REGISTERS AND METHOD THEREFOR 审中-公开
标题翻译：具有空间有效数据寄存器的高度非易失性非易失性存储器及其方法
公开(公告)号：WO2004029977A1
公开(公告)日：2004-04-08
申请号：PCT/US2003/029141
申请日：2003-09-17
申请人： SANDISK CORPORATION
发明人： CERNEA, Raul-Adrian
IPC分类号： G11C7/10
CPC分类号： G11C19/00 , G11C7/1036 , G11C16/10 , G11C16/26 , G11C2211/5642
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. In one aspect, data latches associated with the multiple read/write circuits are I/O enabled and coupled in a compact manner for storage and serial transfer. They are implemented by one or more chain of link modules, which can selectively behave as inverters or latches. A method enables the use of a minimum number of link modules by cycling data between a set of master link modules and a substantially smaller set of slave link modules.
摘要翻译：能够并行读取和写入大量存储器单元的非易失性存储器件具有将多个读/写电路中的冗余降至最低的架构。在一个方面，与多个读/写电路相关联的数据锁存器是以紧凑的方式启用和耦合的I / O进行存储和串行传输。它们由一个或多个链路链路模块实现，链路模块可以选择性地表现为反相器或锁存器。一种方法能够通过在一组主链路模块和较小的一组从属链路模块之间循环数据来使用最少数量的链路模块。

5. 发明申请

WO99014758A1 SENSE AMPLIFIER FOR FLASH MEMORIES 审中-公开
标题翻译：感应放大器用于闪存
公开(公告)号：WO99014758A1
公开(公告)日：1999-03-25
申请号：PCT/US1998/014797
申请日：1998-07-17
IPC分类号： G11C16/06 , G11C7/06 , G11C11/56 , G11C16/02 , G11C16/28 , G11C7/00
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/065 , G11C11/5621 , G11C11/5642 , G11C2211/5642
摘要： A sense amplifier (800) for a nonvolative writeable memory is described. The sense amplifier (800) has preamplifier (802) coupled to receive a signal from a grounded-gate p-channel metal-oxide semiconductor input stage. A differential input latch (804) is coupled to the preamplifier output. The differential input latch (804) uses a pair of cross-coupled inverters. A logic device (806) is coupled to the differential input latch output and provides the sense amplifier output signal. The logic device (806) reduces the offset in the differential input latch (804) and provides an output indicative of one of a number of stages or voltage levels of the cell.
摘要翻译：描述了用于非易失性可写存储器的读出放大器（800）。读出放大器（800）具有耦合以从接地栅p沟道金属氧化物半导体输入级接收信号的前置放大器（802）。差分输入锁存器（804）耦合到前置放大器输出端。差分输入锁存器（804）使用一对交叉耦合的反相器。逻辑器件（806）耦合到差分输入锁存器输出并提供读出放大器输出信号。逻辑器件（806）减小差分输入锁存器（804）中的偏移，并且提供指示单元的多个级或电压电平之一的输出。

6. 发明申请

WO1997048098A1 PAGE MODE FLOATING GATE MEMORY DEVICE STORING MULTIPLE BITS PER CELL 审中-公开
标题翻译：页面模式浮动栅格存储器设备存储每个单元的多个位
公开(公告)号：WO1997048098A1
公开(公告)日：1997-12-18
申请号：PCT/US1996010374
申请日：1996-06-14
申请人： MACRONIX INTERNATIONAL CO., LTD. , HUNG, Chun-Hsiung , WAN, Ray-Lin , CHENG, Yao-Wu
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C07/00
CPC分类号： G11C16/3445 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/3436 , G11C16/3459 , G11C2211/5622 , G11C2211/5642 , G11C2216/14
摘要： An array (10) of multi-level floating gate memory cells includes wordlines (18) connected to memory cells along a row in the array, and bit lines (12) connected to memory cells along a column in the array. A wordline voltage source (27) is included which supplies selectively wordline voltages corresponding to respective threshold voltages of the memory cells in the array. A plurality of bit latches form a page buffer (11). Bit latches are coupled to corresponding bit lines, and have a first state and a second state. The bit latches include circuits (213-216) to change the bit latches from the first state to the second state in response to signals on the corresponding bit lines that are generated in response to a wordline voltage on a selected wordline being greater than or equal to the threshold voltage of a memory cell on the corresponding bit line connected to the selected wordline. Logic (21) controls the wordline voltage source and the bit latches to apply in a sequence the wordline voltages, and to sense the state of the bit latches after applying each wordline voltage in the sequence to determine the threshold voltages of the memory cells.
摘要翻译：多级浮动栅极存储单元的阵列（10）包括连接到阵列中的行的存储单元的字线（18）和沿列阵列的存储单元连接的位线（12）。包括字线电压源（27），其选择性地提供对应于阵列中的存储器单元的各个阈值电压的字线电压。多个位锁存器形成页缓冲器（11）。位锁存器耦合到对应的位线，并且具有第一状态和第二状态。比特锁存器包括响应于所选择的字线上的字线电压响应于相应位线上响应的信号而将位锁存器从第一状态改变到第二状态的电路（213-216）大于或等于到连接到所选字线的相应位线上的存储器单元的阈值电压。逻辑（21）控制字线电压源和位锁存器以序列施加字线电压，并且在施加序列中的每个字线电压以确定存储器单元的阈值电压之后感测位锁存器的状态。

7. 发明申请

WO1997007513A1 MULTI-LEVEL NON-VOLATILE DATA STORAGE 审中-公开
标题翻译：多级非易失性数据存储
公开(公告)号：WO1997007513A1
公开(公告)日：1997-02-27
申请号：PCT/US1996013211
申请日：1996-08-14
申请人： LEXAR MICROSYSTEMS, INC.
发明人： LEXAR MICROSYSTEMS, INC. , ASSAR, Mahmud , KESHTBOD, Parviz
IPC分类号： G11C11/56
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5621 , G11C2211/5634 , G11C2211/5642
摘要： A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.
摘要翻译：多级NAND架构非易失性存储器件通过与恒定电流电平进行比较来读取和编程存储单元，每个存储单元存储多于一位的数据，同时选择性地调整读或编程的单元或单元上的栅极电压。提供多个读取和写入参考单元，每个编程为对应于多级编程中的每一个，其中在读取存储器单元期间，读取的参考单元提供恒定电流电平，并且在写入存储器单元期间，写入参考细胞提供相同的。此外，在读取操作期间，将相应的写入参考单元耦合到读取参考单元以测量与读取存储器单元相关联的读取时间。

8. 发明申请

WO1996008823A1 INTEGRATED CIRCUIT SYSTEM FOR ANALOG SIGNAL STORING AND RECOVERY INCORPORATING READ WHILE WRITING VOLTAGE PROGRAM METHOD 审中-公开
标题翻译：用于模拟信号存储和恢复的集成电路系统在写入电压方案时读取
公开(公告)号：WO1996008823A1
公开(公告)日：1996-03-21
申请号：PCT/US1995011590
申请日：1995-09-13
申请人： INFORMATION STORAGE DEVICES, INC.
发明人： INFORMATION STORAGE DEVICES, INC. , ENGH, Lawrence, D. , BLYTH, Trevor
IPC分类号： G11C11/34
CPC分类号： G11C27/005 , G11C7/16 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5624 , G11C2211/5642
摘要： An integrated circuit which operates to store an input analog signal within an analog storage device such as an EEPROM (108) is disclosed. Initially, a target voltage is determined for applying to the memory cell with the target voltage set to about 90 % of the input analog signal voltage. A high voltage ramp (112) is applied to the memory cell to set the voltage of the cell to the target voltage. A read operation is simultaneously performed while the high voltage ramp is applied to detect the voltage stored on the cell and to terminate the application of the high voltage ramp once the target voltage is reached (104). Thereafter, a normal read operation is performed on the memory cell to detect the actual voltage of the cell. The "read-while writing" operations are performed a predetermined number of times to achieve programming of the cell.
摘要翻译：公开了一种用于将输入模拟信号存储在诸如EEPROM（108）的模拟存储设备内的集成电路。最初，确定目标电压以将目标电压设置为输入模拟信号电压的大约90％来施加到存储单元。将高电压斜坡（112）施加到存储器单元以将电池的电压设置为目标电压。当施加高压斜坡以同时执行读取操作以检测存储在单元上的电压，并且一旦达到目标电压（104）就终止施加高压斜坡。此后，对存储器单元执行正常的读取操作以检测单元的实际电压。执行“读写同时”操作预定次数以实现单元的编程。

9. 发明申请

WO2014137846A1 DEFECT OR PROGRAM DISTURB DETECTION WITH FULL DATA RECOVERY CAPABILITY 审中-公开
标题翻译：缺陷或程序干扰检测具有完整的数据恢复能力
公开(公告)号：WO2014137846A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/019730
申请日：2014-03-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： DUTTA, Deepanshu , LEE, Dana , LI, Yan , SHAH, Grishma , MOOGAT, Farookh , HIGASHITANI, Masaaki
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C2211/5621 , G11C2211/5642
摘要： A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.
摘要翻译：用于一组非易失性存储元件的编程操作在程序验证测试通过并且发出程序状态=通过之后确定存储元件是否已经被正确编程。使用可选的一个或多个重建读取操作的逻辑运算，从与存储元件相关联的锁存器组重建写入数据。还执行正常读取操作以获得读取数据。确定读取数据和重建的写入数据之间的一些不匹配，并且基于不匹配的数量确定是否需要重写写入数据。

10. 发明申请

WO2014074131A1 NAND FLASH BASED CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：基于NAND FLASH的内容可寻址存储器
公开(公告)号：WO2014074131A1
公开(公告)日：2014-05-15
申请号：PCT/US2013/026171
申请日：2013-02-14
申请人： SANDISK TECHNOLOGIES INC.
发明人： SPROUSE, Stephen, T.
IPC分类号： G11C15/04 , G11C16/04
CPC分类号： G06F12/0246 , G11C11/5642 , G11C15/046 , G11C16/02 , G11C16/0483 , G11C16/3459 , G11C2211/5641 , G11C2211/5642 , G11C2213/71 , G11C2213/75
摘要： A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.
摘要翻译：基于NAND Flash的内容可寻址存储器（CAM）用于键值寻址存储驱动器。该设备可以使用标准传输协议，如PCI-E，SAS，SATA，eMMC，SCSI等。主机向驱动器写入键值对，驱动器将驱动器沿着驱动器的CAM NAND部分的位线写入键，并将该值存储在驱动器中。然后，驱动器维护将键链接到值的位置的表。在读取过程中，主机提供驱动键，然后将存储键的块的字线广播下来。基于任何匹配的位线，然后可以使用表来检索并将相应的数据提供给主机。

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