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1. 发明申请

WO2015017281A1 SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY 审中-公开
标题翻译：用于垂直位线阵列的共享垂直TFT
公开(公告)号：WO2015017281A1
公开(公告)日：2015-02-05
申请号：PCT/US2014/048259
申请日：2014-07-25
申请人： SANDISK 3D LLC
发明人： YAN, Tianhong , SAMACHISA, George , LIU, Tz-yi , CHEN, Tim , RATNAM, Perumal
IPC分类号： H01L27/06 , G11C7/18 , G11C11/56 , G11C13/00 , H01L29/788 , H01L27/115
CPC分类号： G11C13/0069 , G11C7/18 , G11C13/0002 , G11C13/0023 , G11C13/003 , G11C2013/0073 , G11C2013/0083 , G11C2207/005 , G11C2213/15 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/0688 , H01L27/101 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an "on" condition for the double gated vertically oriented select devices to be activated.
摘要翻译：非易失性存储装置包括：基板; 存储单元的单片三维阵列; 连接到存储单元的字线; 全局位线连接到存储单元的垂直位线; 和多个双门控垂直取向选择装置。双门控垂直取向的选择装置连接到垂直位线和全局位线，使得当双门控垂直取向的选择装置被激活时，垂直位线与全局位线通信。每个双门控垂直取向的选择装置具有两个相对于到衬底的距离彼此偏移的栅极。双门控垂直取向选择装置的两个门都需要处于“开启”状态，双门控垂直取向的选择装置被激活。

2. 发明申请

WO2012118618A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 审中-公开
标题翻译：具有柱管的三维存储系统
公开(公告)号：WO2012118618A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/025171
申请日：2012-02-15
申请人： SANDISK 3D LLC , YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
发明人： YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
IPC分类号： G11C7/10 , G11C7/18 , G11C13/00 , G11C17/16
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的顶列和位于相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

3. 发明申请

WO2010123517A1 MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEME 审中-公开
标题翻译：具有数据线切换方案的存储器系统
公开(公告)号：WO2010123517A1
公开(公告)日：2010-10-28
申请号：PCT/US2009/058889
申请日：2009-09-29
申请人： SANDISK 3D LLC , YAN, Tianhong , FASOLI, Luca
发明人： YAN, Tianhong , FASOLI, Luca
IPC分类号： G11C8/12 , G11C13/00
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了增加存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。独立检测每组的第一非易失性存储元件的存储器操作的完成。在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

4. 发明申请

WO2010117914A1 THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A SINGLE-SIDED WORD LINE ARCHITECTURE 审中-公开
标题翻译：具有垂直位线和单面字线结构的可重新编程的非易失性存储器元件的三维阵列
公开(公告)号：WO2010117914A1
公开(公告)日：2010-10-14
申请号：PCT/US2010/029857
申请日：2010-04-02
申请人： SANDISK 3D LLC , SAMACHISA, George , YAN, Tianhong
发明人： SAMACHISA, George , YAN, Tianhong
IPC分类号： G11C8/14 , G11C13/00 , G11C7/18 , H01L27/24
CPC分类号： G11C13/0007 , G11C7/18 , G11C8/14 , G11C13/0028 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/77 , H01L27/2436 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
摘要翻译：特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。单面字线架构为每行存储器元件专门提供字线，而不是在两行存储器元件之间共享一个字线，从而避免跨越字线跨越阵列链接存储元件。虽然存储器元件行也被对应的局部位线行访问，但是在局部位线的相邻行之间没有扩展耦合，因此没有扩展超出字线的漏电流。

5. 发明申请

WO2009158676A1 CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY 审中-公开
标题翻译：用于写入非易失性存储器的电容式放电方法
公开(公告)号：WO2009158676A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048955
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
IPC分类号： G11C13/00 , G11C7/22
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路元素。用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

6. 发明申请

WO2009158670A1 REVERSE SET WITH CURRENT LIMIT FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：随着非易失性存储的电流限制反向设置
公开(公告)号：WO2009158670A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048945
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , YAN, Tianhong
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.
摘要翻译：存储系统包括衬底，衬底上的控制电路，包括多个可逆电阻开关元件的三维存储器阵列（衬底上方），以及用于限制可逆电阻切换元件的SET电流的电路。以反向偏置的方式对存储器单元进行SET设置。

7. 发明申请

WO2016053533A1 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS 审中-公开
标题翻译：用于传感硬头和软件位置的装置和方法
公开(公告)号：WO2016053533A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/047626
申请日：2015-08-30
申请人： SANDISK 3D LLC
发明人： SIAU, Chang , LEE, Jeffrey Koon Yee , YAN, Tianhong , CHEN, Yingchang , BALAKRISHNAN, Gopinath , LIU, Tz-Yi
IPC分类号： G11C11/16 , G11C13/00 , G11C16/28 , G11C16/32
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a hard bit and N soft bits of a memory cell of a nonvolatile memory system in response to a single read command in a total time corresponding to a single read latency period and N + 1 data transfer times, the method comprising: generating a sense signal proportional to a current of the memory cell; generating a reference signal that comprises 2N + 1 distinct reference signal values; generating a comparison signal by comparing the sense signal and the reference signal; sampling the comparison signal to generate 2N + 1 data values; and determining the hard bit and the N soft bits based on the 2N + 1 data values.
摘要翻译：提供了一种用于在对应于单个读等待时间周期和N + 1个数据传送时间的总时间内响应于单个读取命令来读取非易失性存储器系统的存储器单元的硬比特和N个软比特的方法，该方法包括：产生与所述存储器单元的电流成比例的感测信号; 生成包括2N + 1个不同参考信号值的参考信号; 通过比较感测信号和参考信号来产生比较信号; 对比较信号进行采样以产生2N + 1个数据值; 以及基于2N + 1个数据值来确定硬比特和N个软比特。

8. 发明申请

WO2015148399A1 NON-VOLATILE 3D MEMORY WITH CELL-SELECTABLE WORD LINE DECODING 审中-公开
标题翻译：非易失性3D存储器，具有细胞选择性字线解码
公开(公告)号：WO2015148399A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022060
申请日：2015-03-23
申请人： SANDISK 3D LLC
发明人： YAN, Tianhong , SCHEUERLEIN, Roy E.
IPC分类号： H01L27/24
CPC分类号： G11C13/0021 , G11C5/025 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/249
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line (WL) in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines (331, 332) through the multiple layers of planes. The pillar lines are of a first type (331) that act as local bit lines and a second type (332) that provide access to the word lines by having respective memory elements (348) preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储器元件各自可以通过平面中的字线（WL）和本地位线来访问。三维阵列包括穿过多层平面的柱线（331,332）的二维阵列。柱线是用作局部位线的第一类型（331）和第二类型（332），其通过将各自的存储元件（348）预设为永久低电阻状态来提供对字线的访问，用于专用于相应字线的支柱线。衬底上的金属线阵列可切换地连接到垂直位线以提供对局部位线和字线的访问。

9. 发明申请

WO2011156343A2 NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF 审中-公开
标题翻译：具有读取/写入元件的3D阵列的非易失性存储器及其读取/写入电路及其方法
公开(公告)号：WO2011156343A2
公开(公告)日：2011-12-15
申请号：PCT/US2011/039405
申请日：2011-06-07
申请人： SANDISK 3D LLC , SAMACHISA, George , FASOLI, Luca , LI, Yan , YAN, Tianhong
发明人： SAMACHISA, George , FASOLI, Luca , LI, Yan , YAN, Tianhong
IPC分类号： G11C11/16 , G11C13/02
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0097 , G11C16/06 , G11C2013/0054 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
摘要翻译：三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

10. 发明申请

WO2015179537A1 INTRINSIC VERTICAL BIT LINE ARCHITECTURE 审中-公开
标题翻译：内部垂直位线架构
公开(公告)号：WO2015179537A1
公开(公告)日：2015-11-26
申请号：PCT/US2015/031804
申请日：2015-05-20
申请人： SANDISK 3D LLC
发明人： RATNAM, Perumal , PETTI, Christopher , YAN, Tianhong
IPC分类号： G11C7/18 , G11C13/00 , H01L27/24
CPC分类号： G11C13/0026 , G11C7/18 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1226 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

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