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1. 发明申请

WO2014133979A1 DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法
公开(公告)号：WO2014133979A1
公开(公告)日：2014-09-04
申请号：PCT/US2014/018123
申请日：2014-02-25
申请人： SANDISK 3D LLC
发明人： BANDYOPADHYAY, Abhijit , KUMAR, Tanmay , HERNER, Scott Brad , PETTI, Christopher J. , SCHEUERLEIN, Roy E.
IPC分类号： H01L27/102 , G11C17/16 , H01L27/24 , G11C11/56 , H01L45/00 , H01L29/861
CPC分类号： G11C17/165 , G11C11/5692 , G11C17/18 , H01L27/1021 , H01L27/11206 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.
摘要翻译：在一些方面，提供了包括转向元件和存储元件的存储单元。存储元件包括第一导电材料层，设置在第一导电材料层上方的第一介电材料层，设置在第一介电材料层上方的第二导电材料层，设置在第二导电材料层上方的第二介电材料层，以及设置在所述第二介电材料层上方的第三导电材料层。第一导电材料层和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的堆叠。提供了许多其他方面。

2. 发明申请

WO2007008344A1 INTEGRATED CIRCUIT EMBODYING A NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：集成电路构造非易失性存储器单元
公开(公告)号：WO2007008344A1
公开(公告)日：2007-01-18
申请号：PCT/US2006/023705
申请日：2006-06-19
申请人： SANDISK 3D LLC , BANDYOPADHYAY, Abhijit , PETTI, Christopher J. , KUMAR, Tanmay
发明人： BANDYOPADHYAY, Abhijit , PETTI, Christopher J. , KUMAR, Tanmay
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788
CPC分类号： H01L29/7883 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5µm from a diffusion region of the capacitor.
摘要翻译：提供了包括至少一个存储单元的集成电路。这样的存储单元又包括晶体管和电容器。晶体管包括源极，漏极和栅极。此外，电容器包括阱和栅极。晶体管的栅极保持与电容器的栅极通信。在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。在这样的实施例中，晶体管的阱邻接电容器的阱。在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

3. 发明申请

WO2006105435A1 TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 审中-公开
标题翻译：用于紧凑的内存阵列的晶体管布局配置
公开(公告)号：WO2006105435A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/012039
申请日：2006-03-31
申请人： SANDISK 3D LLC , PETTI, Christopher J. , SCHEUERLEIN, Roy E. , KUMAR, Tanmay , BANDYOPADHYAY, Abhijit
发明人： PETTI, Christopher J. , SCHEUERLEIN, Roy E. , KUMAR, Tanmay , BANDYOPADHYAY, Abhijit
IPC分类号： G01J1/12
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。

4. 发明申请

WO2008016932A3 METHOD AND APPARATUS FOR PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 审中-公开
公开(公告)号：WO2008016932A3
公开(公告)日：2008-02-07
申请号：PCT/US2007/074883
申请日：2007-07-31
申请人： SANDISK 3D LLC , FASOLI, Luca G. , PETTI, Christopher J. , SCHEUERLEIN, Roy E.
发明人： FASOLI, Luca G. , PETTI, Christopher J. , SCHEUERLEIN, Roy E.
IPC分类号： G11C11/00
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

5. 发明申请

WO2006104817A2 METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES 审中-公开
标题翻译：在制造与导电特性接触时减少电介质覆盖物的方法
公开(公告)号：WO2006104817A2
公开(公告)日：2006-10-05
申请号：PCT/US2006/010520
申请日：2006-03-21
申请人： SANDISK 3D, LLC , PETTI, Christopher J.
发明人： PETTI, Christopher J.
IPC分类号： H01L21/768 , H01L27/102
CPC分类号： H01L21/768 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.
摘要翻译：在本发明的第一优选实施例中，导电特征形成在第一电介质蚀刻停止层上，并且第二电介质材料沉积在导电特征之上和之间。在第一和第二电介质之间选择性的导电特征的通孔蚀刻将停止在电介质蚀刻停止层上，限制过蚀刻。在第二实施例中，多个导电特征以消减图案和蚀刻工艺形成，填充有电介质填充物，然后形成为与导电特征和电介质填充物共同构成的表面。电介质蚀刻停止层沉积在表面上，然后第三电介质覆盖电介质蚀刻停止层。当通过第三电介质蚀刻接触时，该选择性蚀刻停止在电介质蚀刻停止层上。第二蚀刻与导电特征接触。

6. 发明申请

WO2011056527A2 METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 审中-公开
标题翻译：用于降低成本图案的三维矩阵阵列存储器布局方法和装置
公开(公告)号：WO2011056527A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/054013
申请日：2010-10-26
申请人： SANDISK 3D, LLC , SCHEUERLEIN, Roy E. , PETTI, Christopher J. , TANAKA, Yoichiro
发明人： SCHEUERLEIN, Roy E. , PETTI, Christopher J. , TANAKA, Yoichiro
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了用于三维存储器的存储层布局的装置，方法和系统。存储器层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储器线; 以及用于将存储器层耦合到三维存储器中的其他存储器层的多个齐触点区域。存储器线从存储器阵列块延伸并且使用侧壁限定的过程形成。存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。齐亚接触区的尺寸大约是存储器线的半间距尺寸的四倍。存储器线被布置成适合于允许单个存储器线与单个zia接触区相交并且为其他zia接触区提供其他存储器线之间的区域的图案。披露了许多其他方面。

7. 发明申请

WO2006104877A3 METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE 审中-公开
公开(公告)号：WO2006104877A3
公开(公告)日：2006-10-05
申请号：PCT/US2006/010757
申请日：2006-03-24
申请人： SANDISK 3D, LLC , DUNTON, Samuel V. , RAGHURAM, Usha , PETTI, Christopher J.
发明人： DUNTON, Samuel V. , RAGHURAM, Usha , PETTI, Christopher J.
IPC分类号： H01L21/768 , H01L21/8246
摘要： A substantially planar surface coexposes conductive or semiconductor features (300) and a dielectric etch, stop material (120). A second dielectric material (107), different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric (108) such, as oxide, recessing the oxide, filling with the dielectric etch stop material such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

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