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41. 发明申请

WO2015030937A1 OFFSET CANCELING DUAL STAGE SENSING CIRCUIT 审中-公开
标题翻译：偏移取消双级传感电路
公开(公告)号：WO2015030937A1
公开(公告)日：2015-03-05
申请号：PCT/US2014/046048
申请日：2014-07-09
申请人： QUALCOMM INCORPORATED , INDUSTRY-ACADEMIC COOPERATION FOUNDATION
发明人： JUNG, Seong-Ook , NA, Taehui , KIM, Jisu , KIM, Jung Pill , KANG, Seung Hyuk
IPC分类号： G11C13/00 , G11C11/16 , H03K3/356 , H03K3/37 , G11C7/06
CPC分类号： G11C11/1673 , G11C7/06 , G11C7/065 , G11C11/1693 , G11C13/004 , G11C2013/0054 , G11C2013/0057
摘要： An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.
摘要翻译：偏移消除双级感测方法包括使用在第一级操作中由电阻性存储器参考单元的参考值产生的第一负载PMOS栅极电压来感测电阻性存储器数据单元的数据值。该方法还包括使用在电阻性存储器感测电路的第二级操作中由电阻性存储器数据单元的数据值产生的第二负载PMOS栅极电压来感测电阻性存储器参考单元的参考值。通过调整参考单元感测的工作点，与常规感测电路相比，偏移消除双级感测电路显着增加了感测余量。

42. 发明申请

WO2014182449A1 ELECTROSTATIC DISCHARGE DIODE 审中-公开
标题翻译：静电放电二极管
公开(公告)号：WO2014182449A1
公开(公告)日：2014-11-13
申请号：PCT/US2014/035076
申请日：2014-04-23
申请人： QUALCOMM INCORPORATED
发明人： RAMACHANDRAN, Vidhya , HENDERSON, Brian M. , GU, Shiqun , TAN, Chiew-Guan , KIM, Jung Pill , KIM, Taehyun
IPC分类号： H01L27/06 , H01L23/48 , H01L23/60 , H01L25/065 , H01L27/02
CPC分类号： H01L29/66128 , H01L21/304 , H01L21/762 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/535 , H01L23/60 , H01L25/0657 , H01L27/0255 , H01L27/0296 , H01L27/0694 , H01L27/0814 , H01L29/0649 , H01L29/66143 , H01L29/8611 , H01L29/872 , H01L2224/02372 , H01L2224/0239 , H01L2224/0401 , H01L2224/05548 , H01L2224/0557 , H01L2224/11002 , H01L2224/13022 , H01L2224/13024 , H01L2224/16145 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12032 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要： A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.
摘要翻译：一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。该方法还包括在衬底的背面形成第一二极管。第一二极管耦合到第一通孔。

43. 发明申请

WO2014130301A1 STT-MRAM DESIGN ENHANCED BY SWITCHING CURRENT INDUCED MAGNETIC FIELD 审中-公开
标题翻译：通过切换电流感应磁场增强STT-MRAM设计
公开(公告)号：WO2014130301A1
公开(公告)日：2014-08-28
申请号：PCT/US2014/015858
申请日：2014-02-11
申请人： QUALCOMM INCORPORATED
发明人： XIA, William H. , WU, Wenqing , YUEN, Kendrick H. , BANERJEE, Abhishek , LI, Xia , KANG, Seung H. , KIM, Jung Pill
IPC分类号： H01L43/02 , H01L43/08 , H01L43/12
CPC分类号： H01L43/02 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1693 , H01L43/08 , H01L43/12
摘要： A memory cell (200) includes an elongated first electrode (206) coupled to a magnetic tunnel junction (MTJ) structure (210) and an elongated second electrode (212) aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.
摘要翻译：存储单元（200）包括耦合到磁隧道结（MTJ）结构（210）的细长第一电极（206）和与耦合到MTJ结构的细长第一电极对准的细长第二电极（212）。细长电极被配置为引导开关电流感应磁场的相互添加部分通过MTJ。响应于开关电流的应用，相互添加的部分增强了MTJ的切换。

44. 发明申请

WO2014043578A1 OTP CELL WITH REVERSED MTJ CONNECTION 审中-公开
标题翻译：具有反向MTJ连接的OTP单元
公开(公告)号：WO2014043578A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/059812
申请日：2013-09-13
申请人： QUALCOMM INCORPORATED
发明人： KIM, Jung Pill , KIM, Taehyun , LEE, Kangho , KAN, Seung H. , LI, Xia , HSU, Wah Nam
IPC分类号： G11C11/16 , G11C17/02 , G11C17/16
CPC分类号： G11C17/18 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C17/165
摘要： A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.
摘要翻译：一次编程（OTP）装置单元包括具有反向连接的磁隧道结（MTJ），用于在编程期间将MTJ置于反并联电阻状态。在其反并联电阻状态下增加的MTJ电阻会导致更高的编程电压，从而减少编程时间和编程电流。

45. 发明申请

WO2014039571A1 MRAM WORD LINE POWER CONTROL SCHEME 审中-公开
标题翻译： MRAM WORD线路功率控制方案
公开(公告)号：WO2014039571A1
公开(公告)日：2014-03-13
申请号：PCT/US2013/058081
申请日：2013-09-04
申请人： QUALCOMM INCORPORATED
发明人： KIM, Sungryul , KIM, Jung Pill , KIM, Taehyun , KANG, Seung H. , NOWAK, Matthew M. , BHATNAGAR, Manoj
IPC分类号： G11C11/16 , G11C8/08
CPC分类号： G11C11/165 , G11C8/08 , G11C11/16 , G11C11/1653 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/1697
摘要： Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro.
摘要翻译：用于控制磁阻随机存取存储器（MRAM）的WL处的字线（WL）功率电平的系统，电路和方法。所公开的功率控制方案使用现有的读/写命令和与MRAM相关联的现有发电模块来提供和控制WL功率电平，从而消除通过相对大且昂贵的功率来控制WL功率的方案的成本和增加的裸片尺寸控制开关和MRAM宏上的控制电路。

46. 发明申请

WO2014031442A1 MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGENTIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS 审中-公开
标题翻译：多级记忆体细胞使用多变磁场隧道结与不同的MGO厚度
公开(公告)号：WO2014031442A1
公开(公告)日：2014-02-27
申请号：PCT/US2013/055171
申请日：2013-08-15
申请人： QUALCOMM INCORPORATED
发明人： LEE, Kangho , KIM, Taehyun , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16 , G11C11/56
CPC分类号： G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/5607 , H01L21/00
摘要： A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures (MTJ1, MTJ2) having one or more layers with varying thickness is disclosed. The multiple MTJ structures (MTJ1, MTJ2), which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures (MTJ1, MTJ2). Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures (MTJ1, MTJ2) with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers (46a, 46b, 56a, 56b) associated with the multiple MTJ structures (MTJ1, MTJ2) and/or free layers (48a, 48b, 58a, 58b) associated with the multiple MTJ structures (MTJ1, MTJ2).
摘要翻译：公开了使用具有一层或多层具有变化厚度的多个磁隧道结（MTJ）结构（MTJ1，MTJ2）的多层存储单元（MLC）。垂直堆叠和串联布置的多个MTJ结构（MTJ1，MTJ2）可以具有基本上相同的面积尺寸以最小化制造成本，因为可以使用一个掩模来对多个MTJ结构（MTJ1，MTJ2）进行图案化。此外，改变与一个或多个层相关联的厚度可以提供具有不同开关电流密度的多个MTJ结构（MTJ1，MTJ2），从而增加存储器密度并改善读和写操作。在一个实施例中，具有变化厚度的层可以包括与多个MTJ结构（MTJ1，MTJ2）和/或自由层（48a，48b，58a，...）相关联的隧道势垒或氧化镁层（46a，46b，56a，56b） 58b）与多个MTJ结构（MTJ1，MTJ2）相关联。

47. 发明申请

WO2013166479A1 A TUNABLE REFERENCE CIRCUIT COMPRISING MAGNETIC TUNNEL JUNCTION ELEMENTS FOR A SEMICONDUCTOR MEMORY CIRCUIT 审中-公开
标题翻译：包含用于半导体存储器电路的磁性连接元件的可控参考电路
公开(公告)号：WO2013166479A1
公开(公告)日：2013-11-07
申请号：PCT/US2013/039656
申请日：2013-05-06
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , KIM, Jung Pill , KIM, Taehyun
IPC分类号： G11C11/16 , G11C11/56 , G11C7/06
CPC分类号： G11C7/062 , G11C11/16 , G11C11/1673 , G11C11/5642
摘要： A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements.
摘要翻译：电路包括包括第一路径和第二路径的第一参考对。第一路径包括第一磁隧道结（MTJ）元件，第二路径包括第二MTJ元件。电路还包括第二参考对，其包括第三路径和第四路径。第三路径包括第三MTJ元件，第四路径包括第四MTJ元件。第一个参考对和第二个参考对并联在一起。电路的参考电阻基于第一，第二，第三和第四MTJ元件中的每一个的电阻。通过调整MTJ元件之一的电阻可以调节电路的参考电阻。

48. 发明申请

WO2013059808A1 SYSTEM AND METHOD FOR MRAM HAVING CONTROLLED AVERAGABLE AND ISOLATABLE VOLTAGE REFERENCE 审中-公开
标题翻译：具有可控制和可分离电压参考的MRAM的系统和方法
公开(公告)号：WO2013059808A1
公开(公告)日：2013-04-25
申请号：PCT/US2012/061359
申请日：2012-10-22
申请人： QUALCOMM INCORPORATED
发明人： KIM, Jung Pill , KIM, Taehyun
IPC分类号： G11C5/06 , G11C7/08 , G11C29/02
CPC分类号： G11C13/004 , G11C5/063 , G11C7/08 , G11C11/1673 , G11C13/0038 , G11C13/0069 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.
摘要翻译：存储器具有多个非易失性电阻（NVR）存储器阵列，每个存储阵列具有通过参考电路耦合链路耦合到参考线的相关联的参考电压产生电路，该参考耦合到用于该NVR存储器阵列的读出放大器。参考线耦合链路耦合不同NVR存储器阵列的参考线。可选地，不同的参考耦合链路被去除或打开，在不同的参考线上获得各自不同的平均和隔离参考电压。可选地，去除或打开不同的参考电路耦合链路，在参考线上获得各自不同的平均电压，以及解耦和隔离不同的参考电路。

49. 发明申请

WO2011119645A2 METHOD AND APPARATUS TO PROVIDE A CLOCK SIGNAL TO A CHARGE PUMP 审中-公开
标题翻译：向充电泵提供时钟信号的方法和装置
公开(公告)号：WO2011119645A2
公开(公告)日：2011-09-29
申请号：PCT/US2011/029481
申请日：2011-03-22
申请人： QUALCOMM Incorporated , HAO, Wuyang , KIM, Jung Pill , SUH, Jungwon
发明人： HAO, Wuyang , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G06F17/50 , G05F3/02 , G06F1/10
CPC分类号： G06F1/06 , H02M3/07 , H02M3/073 , H02M2003/077
摘要： A method and apparatus for providing a clock signal to a charge pump is disclosed. In a particular embodiment, the method includes providing a first clock signal to a first charge pump unit of a charge pump. The method further includes providing a second clock signal to a second charge pump unit of the charge pump. A low-to-high transition of the first clock signal occurs substantially concurrently with a high-to-low transition of the second clock signal. Only one clock signal may be at a logic high voltage level at any given time.
摘要翻译：公开了一种用于向电荷泵提供时钟信号的方法和装置。在特定实施例中，该方法包括向电荷泵的第一电荷泵单元提供第一时钟信号。该方法还包括向电荷泵的第二电荷泵单元提供第二时钟信号。第一时钟信号的从低到高的跃迁与第二时钟信号的高到低的跃迁基本同时发生。在任何给定时间，只有一个时钟信号可能处于逻辑高电压电平。

50. 发明申请

WO2017039965A1 HARDWARE-ACCELERATED STORAGE COMPRESSION 审中-公开
标题翻译：硬件加速存储压缩
公开(公告)号：WO2017039965A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/046019
申请日：2016-08-08
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , KIM, Jung Pill
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/061 , G06F3/064 , G06F3/0644 , G06F3/0665 , G06F3/0685
摘要： Hardware-accelerated storage compression is disclosed. In one aspect, prior to writing an uncompressed data block to a storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data block into a compressed data block and allocates the compressed data block to a physical data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data block. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block. By performing hardware-accelerated storage compression in the storage controller, it is possible to reduce processing overhead associated with conventional software-based compression systems and improve compression control over conventional storage-device-driven compression systems.
摘要翻译：公开了硬件加速存储压缩。一方面，在将未压缩数据块写入存储装置之前，设置在存储控制器中的硬件压缩加速器将未压缩数据块压缩为压缩数据块，并将压缩数据块分配给存储装置中的物理数据块。硬件压缩加速器然后生成修改的逻辑块地址（LBA），以将未压缩的数据块链接到压缩数据块。在另一方面，硬件压缩加速器基于相应的修改的LBA定位压缩数据块，并将压缩数据块解压缩为未压缩的数据块。通过在存储控制器中执行硬件加速存储压缩，可以减少与传统的基于软件的压缩系统相关联的处理开销，并且改进对传统的存储设备驱动的压缩系统的压缩控制。

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