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1. 发明申请

WO2017112348A1 PHASE CHANGE MEMORY DEVICES AND SYSTEMS HAVING REDUCED THRESHOLD VOLTAGE DRIFT AND ASSOCIATED METHODS 审中-公开
标题翻译：具有降低的阈值电压漂移的相变存储器件和系统以及相关方法
公开(公告)号：WO2017112348A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063797
申请日：2016-11-26
申请人： INTEL CORPORATION
发明人： ROBUSTELLI, Mattia
IPC分类号： G11C13/00
CPC分类号： G11C13/0033 , G06F13/1657 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2213/76
摘要： Phase change memory devices, systems, and associated methods are provided and described. Such devices, systems, and methods manage and reduce voltage threshold drift of a phase change memory device comprising a select device SD and a phase change memory element PM, by at least reducing the threshold voltage drift of the select device SD, to increase read accuracy of phase change memory.
摘要翻译：提供并描述了相变存储器装置，系统和相关方法。通过至少降低选择器件SD的阈值电压漂移，这样的器件，系统和方法管理并降低包括选择器件SD和相变存储器元件PM的相变存储器件的电压阈值漂移，以提高读取精度的相变记忆体。

2. 发明申请

WO2014150791A3 READING A MEMORY CELL USING A REFERENCE CELL AND A COMMON SENSING PATH 审中-公开
标题翻译：使用参考电池和普通感光路阅读记忆体
公开(公告)号：WO2014150791A3
公开(公告)日：2014-11-13
申请号：PCT/US2014024245
申请日：2014-03-12
申请人： QUALCOMM INC , UNIV YONSEI IACF
发明人： JUNG SEONG-OOK , NA TAEHUI , KIM JISU , KANG SEUNG H , KIM JUNG PILL
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1693 , G11C13/004 , G11C27/024 , G11C2013/0054 , G11C2013/0057 , G11C2207/002
摘要： A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.
摘要翻译：一种方法包括感测数据单元的状态以产生数据电压。数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。该方法还包括感测参考单元的状态以产生参考电压。通过公共感测路径来检测数据单元的状态和参考单元的状态。该方法还包括基于数据电压和参考电压来确定数据单元的逻辑值。

3. 发明申请

WO2013095385A1 APPARATUS AND METHOD FOR PHASE CHANGE MEMORY DRIFT MANAGEMENT 审中-公开
标题翻译：相位变化管理的设备和方法
公开(公告)号：WO2013095385A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066179
申请日：2011-12-20
申请人： INTEL CORPORATION , RAMANUJAN, Raj K. , SCHMISSEUR, Mark A.
发明人： RAMANUJAN, Raj K. , SCHMISSEUR, Mark A.
IPC分类号： G11C13/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C2013/0054 , G11C2013/0057
摘要： A system and method are described for selecting a demarcation voltage for read and write operations. Embodiments of the invention provide a scheme to use multiple VDMs to cover the case where power-on drift is different from power-off drift of the PCMS cells. The controller automatically manages this through tracking refreshes and writes. In addition, the embodiments of the invention provide an efficient scheme to reduce the performance impact of the penalty box following a write by tracking recent write addresses through a hash-table or similar scheme. By way of example, a method in accordance with one embodiment comprises: detecting a read operation directed to a first block of a PCMS memory; determining whether a write operation has previously occurred to the first block within a specified amount of time prior to the read operation; using a first demarcation voltage (VDM) for the read operation if the write operation has previously occurred to the first block within the specified amount of time prior to the write operation; and using a second VDM for the read operation if the write operation has not previously occurred to the first block within the specified amount of time prior to the write or refresh operation.
摘要翻译：描述了用于选择用于读取和写入操作的分界电压的系统和方法。本发明的实施例提供了使用多个VDM来覆盖上电漂移与PCMS单元的断电漂移不同的情况的方案。控制器通过跟踪刷新和写入自动进行管理。此外，本发明的实施例提供了一种有效的方案，以通过通过散列表或类似方案跟踪最近的写入地址来减少写入之后的惩罚盒的性能影响。作为示例，根据一个实施例的方法包括：检测针对PCMS存储器的第一块的读取操作; 在所述读取操作之前的指定时间内确定是否先前对所述第一块发生了写入操作; 如果在写操作之前的指定时间内先前已经对第一块发生写操作，则使用第一分界电压（VDM）作为读操作; 以及如果在所述写入或刷新操作之前的所述指定时间量内的所述第一块以前没有发生写入操作，则使用第二VDM进行所述读取操作。

4. 发明申请

WO2013075102A1 HYBRID READ SCHEME FOR SPIN TORQUE MRAM 审中-公开
标题翻译：用于旋转扭矩MRAM的混合读取方案
公开(公告)号：WO2013075102A1
公开(公告)日：2013-05-23
申请号：PCT/US2012/065852
申请日：2012-11-19
申请人： EVERSPIN TECHNOLOGIES INC.
发明人： ALAM, Syed M. , ANDRE, Thomas , SUBRAMANIAN, Chitra
IPC分类号： G11C11/00
CPC分类号： G11C11/1673 , G11C11/1675 , G11C13/004 , G11C2013/0057
摘要： A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.
摘要翻译：一种从自旋转矩磁阻存储器阵列中的多个位读取数据的方法包括执行一个或多个参考的比特的读取操作，并执行自参考的读取操作，例如破坏性的自参考读取操作，通过引用的读取操作未成功读取的任何位。引用的读取操作可以在破坏性自引用读操作的同时或之前启动。

5. 发明申请

WO2012067667A1 CIRCUIT AND METHOD FOR READING A RESISTIVE SWITCHING DEVICE IN AN ARRAY 审中-公开
标题翻译：用于读取阵列中的电阻式切换装置的电路和方法
公开(公告)号：WO2012067667A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/026496
申请日：2011-02-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C13/004 , G11C13/0007 , G11C27/02 , G11C27/024 , G11C2013/0054 , G11C2013/0057
摘要： A read circuit for sensing a resistive state of a resistive switching device in a crosspoint array has an equipotential preamplifier connected to a selected column line of the resistive switching device in the array to deliver a read current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit includes a reference voltage generation component for generating the reference voltage for the equipotential preamplifier. The reference voltage generation component samples the biasing voltage via the selected column line and adds a small increment to a sampled biasing voltage to form the reference voltage.
摘要翻译：用于感测交叉点阵列中的电阻式开关装置的电阻状态的读取电路具有连接到阵列中的电阻式开关装置的选定列线的等电位前置放大器，以传送读取电流，同时将选定的列线保持在参考电压靠近施加到阵列的未选择行线的偏置电压。读取电路包括用于产生等电位前置放大器的参考电压的参考电压产生部件。参考电压产生组件通过所选列线对偏置电压进行采样，并将一个小增量加到采样的偏置电压上，以形成参考电压。

6. 发明申请

WO2011066584A1 RESISTANCE BASED MEMORY CIRCUIT WITH DIGITAL SENSING 审中-公开
标题翻译：基于电阻的数字信号处理电路
公开(公告)号：WO2011066584A1
公开(公告)日：2011-06-03
申请号：PCT/US2010/058451
申请日：2010-11-30
申请人： QUALCOMM Incorporated , RAO, Hari
发明人： RAO, Hari
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C13/0004 , G11C2013/0054 , G11C2013/0057 , G11C2207/066
摘要： A method of sensing a data value stored at a resistance based memory is disclosed. The method includes receiving a data signal from a data cell. The data cell includes a resistance based memory element. A reference signal is received from a reference circuit. The reference circuit includes a resistance based memory element. The data signal is converted to a data output signal having a first frequency. The reference signal is converted to a reference output signal having a second frequency. A first output signal is generated when the first frequency exceeds the second frequency. A second output signal is generated when the second frequency exceeds the first frequency.
摘要翻译：公开了一种感测存储在基于电阻的存储器中的数据值的方法。该方法包括从数据单元接收数据信号。数据单元包括基于电阻的存储元件。从参考电路接收参考信号。参考电路包括基于电阻的存储元件。数据信号被转换成具有第一频率的数据输出信号。参考信号被转换为具有第二频率的参考输出信号。当第一频率超过第二频率时，产生第一输出信号。当第二频率超过第一频率时，产生第二输出信号。

7. 发明申请

WO2016076879A1 MEMORY CONTROLLERS 审中-公开
标题翻译：内存控制器
公开(公告)号：WO2016076879A1
公开(公告)日：2016-05-19
申请号：PCT/US2014/065606
申请日：2014-11-14
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： JEON, Yoocharn , IGNOWSKI, James S.
IPC分类号： G11C13/00 , G11C7/10
CPC分类号： G11C13/004 , G06F13/1668 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2213/77
摘要： A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.
摘要翻译：存储器控制器包括电压驱动器和电压比较器。电压驱动器将可变电压施加到交叉开关阵列的所选行，以确定驱动通过所述交叉开关阵列的选定存储单元的第一读取电流的第一测量电压。电压驱动器将可变电压施加到所选择的线，以确定驱动通过所选存储单元的第二读取电流的第二测量电压。电压比较器然后确定第一测量电压和第二测量电压之间的电压差，并将电压差与参考电压差进行比较，以确定所选存储单元的状态。交叉开关阵列包括多条行线，多条列线和多个存储单元。每个存储单元耦合在一行行和一列之间的独特组合。

8. 发明申请

WO2014130604A1 SMART READ SCHEME FOR MEMORY ARRAY SENSING 审中-公开
标题翻译：用于记忆阵列感测的SMART阅读方案
公开(公告)号：WO2014130604A1
公开(公告)日：2014-08-28
申请号：PCT/US2014/017252
申请日：2014-02-20
申请人： SANDISK 3D LLC
发明人： CHEN, Yingchang , LEE, Jeffrey Koon Yee
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C7/06 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C16/26 , G11C2013/0054 , G11C2013/0057
摘要： Methods for reducing variability in bias voltages applied to a plurality of memory cells during a sensing operation caused by IR drops along a word line shared by the plurality of memory cells are described. In some embodiments, IR drops along a shared word line may be reduced by reducing sensing currents associated with memory cells whose state has already been determined during a sensing operation. In one example, once a sense amplifier detects that a memory cell being sensed is in a particular state, then the sense amplifier may disable sensing of the memory cell and discharge a corresponding bit line associated with the memory cell. In some cases, a bit line voltage associated with a memory cell whose state has not already been determined during a first phase of a sensing operation may be increased during a second phase of the sensing operation.
摘要翻译：描述了在由多个存储器单元共享的字线的IR下降引起的感测操作期间减小施加到多个存储单元的偏置电压的变化性的方法。在一些实施例中，可以通过减少与在感测操作期间已经确定其状态的存储器单元相关联的感测电流来减小沿着共享字线的IR降级。在一个示例中，一旦读出放大器检测到被感测的存储器单元处于特定状态，则读出放大器可以禁止对存储器单元的感测并放电与存储器单元相关联的相应位线。在一些情况下，在感测操作的第二阶段期间，与在感测操作的第一阶段尚未确定状态的存储器单元相关联的位线电压可能会增加。

9. 发明申请

WO2014058695A1 DRIFT ACCELERATION IN RESISTANCE VARIABLE MEMORY 审中-公开
标题翻译：电阻可变存储器中的加速缓存
公开(公告)号：WO2014058695A1
公开(公告)日：2014-04-17
申请号：PCT/US2013/063194
申请日：2013-10-03
申请人： MICRON TECHNOLOGY, INC.
发明人： CALDERONNI, Alessandro , FERRO, Massimo , FANTINI, Paolo
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C11/00 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0035 , G11C13/0069 , G11C13/0097 , G11C29/006 , G11C29/50008 , G11C2013/0052 , G11C2013/0057
摘要： The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell.
摘要翻译：本公开包括包括电阻变化存储器中的漂移加速度的装置和方法。许多实施例包括将编程信号施加到电阻可变存储单元以将该单元编程到目标状态，随后将预读信号施加到电阻可变存储单元以加速编程单元电阻的漂移，以及随后向电阻变化存储单元施加读取信号。

10. 发明申请

WO2014047119A1 SELF-BIASING MULTI-REFERENCE FOR SENSING MEMORY CELL 审中-公开
标题翻译：用于感应存储单元的自偏置多参考
公开(公告)号：WO2014047119A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/060310
申请日：2013-09-18
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： MIETUS, David, Francis
IPC分类号： G11C7/06 , G11C7/14 , G11C16/24 , G11C16/28 , G11C13/00
CPC分类号： G11C16/06 , G11C7/06 , G11C7/062 , G11C7/14 , G11C16/24 , G11C16/28 , G11C2013/0057
摘要： Current appearing on a bit-line with no memory cells asserted may be used during a bit-line pre-charge time before a read is performed so as to bias a gate-drain shorted PMOS pull-up device connected between the bit-line and a power supply at a VDD potential. The capacitance connected to the gate of this PMOS pull-up device may be used to "store" the resultant gate-source voltage when the drain is disconnected once the pre-charge time is completed. Once the read operation starts, the current of the PMOS pull-up device that has the "stored" resultant gate-source voltage and the "stored" resultant gate-source voltage itself are re-used as the references, or multi-reference, for sensing the state of an asserted memory cell connected to the bit-line during the read operation thereof.
摘要翻译：在执行读取之前的位线预充电时间期间可能会使用不存在存储单元的位线出现的电流，以便偏置连接在位线与位线之间的栅极 - 漏极短路PMOS上拉器件 VDD电位的电源。连接到该PMOS上拉装置的栅极的电容可以用于在预充电时间完成时漏极断开时“存储”所得到的栅极 - 源极电压。一旦读操作开始，将具有“存储的”合成栅源电压和“存储”的合成栅 - 源电压本身的PMOS上拉器件的电流重新用作参考或多参考，用于感测在其读取操作期间连接到位线的被断言的存储器单元的状态。

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