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1. 发明申请

WO2011119645A2 METHOD AND APPARATUS TO PROVIDE A CLOCK SIGNAL TO A CHARGE PUMP 审中-公开
标题翻译：向充电泵提供时钟信号的方法和装置
公开(公告)号：WO2011119645A2
公开(公告)日：2011-09-29
申请号：PCT/US2011/029481
申请日：2011-03-22
申请人： QUALCOMM Incorporated , HAO, Wuyang , KIM, Jung Pill , SUH, Jungwon
发明人： HAO, Wuyang , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G06F17/50 , G05F3/02 , G06F1/10
CPC分类号： G06F1/06 , H02M3/07 , H02M3/073 , H02M2003/077
摘要： A method and apparatus for providing a clock signal to a charge pump is disclosed. In a particular embodiment, the method includes providing a first clock signal to a first charge pump unit of a charge pump. The method further includes providing a second clock signal to a second charge pump unit of the charge pump. A low-to-high transition of the first clock signal occurs substantially concurrently with a high-to-low transition of the second clock signal. Only one clock signal may be at a logic high voltage level at any given time.
摘要翻译：公开了一种用于向电荷泵提供时钟信号的方法和装置。在特定实施例中，该方法包括向电荷泵的第一电荷泵单元提供第一时钟信号。该方法还包括向电荷泵的第二电荷泵单元提供第二时钟信号。第一时钟信号的从低到高的跃迁与第二时钟信号的高到低的跃迁基本同时发生。在任何给定时间，只有一个时钟信号可能处于逻辑高电压电平。

2. 发明申请

WO2012044640A1 RESISTANCE-BASED MEMORY HAVING TWO-DIODE ACCESS DEVICE 审中-公开
标题翻译：具有两个二极管访问器件的基于电阻的存储器
公开(公告)号：WO2012044640A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/053569
申请日：2011-09-28
申请人： QUALCOMM INCORPORATED , HAO, Wuyang , SUH, Jungwon , LEE, Kangho , KIM, Tae Hyun , KIM, Jung Pill , KANG, Seung H.
发明人： HAO, Wuyang , SUH, Jungwon , LEE, Kangho , KIM, Tae Hyun , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C2213/72 , G11C2213/74
摘要： A resistance -based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line (114) and a sense line (112) to generate a current through a resistance -based memory element (110) via a first diode (116) or a second diode (118). A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.
摘要翻译：基于电阻的存储器具有二极管接入装置。在特定实施例中，一种方法包括偏置位线（114）和感测线（112），以经由第一二极管（116）或第二二极管（118）产生通过基于电阻的存储元件（110）的电流，。第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

3. 发明申请

WO2011143099A1 WRITE ENERGY CONSERVATION IN MEMORY 审中-公开
标题翻译：内存中的写入能量保存
公开(公告)号：WO2011143099A1
公开(公告)日：2011-11-17
申请号：PCT/US2011/035725
申请日：2011-05-09
申请人： QUALCOMM INCORPORATED , RAO, Hari M. , KIM, Jung Pill , KIM, Taehyun , ZHU, Xiaochun , LEE, Kangho , HAO, Wuyang
发明人： RAO, Hari M. , KIM, Jung Pill , KIM, Taehyun , ZHU, Xiaochun , LEE, Kangho , HAO, Wuyang
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1693
摘要： A method writes data to a resistive memory, such as spin torque transfer magnetic random access memory (STT-MRAM). The method writes received bits of data to a memory cell array, in response to a first write signal. The method also reads stored data from the memory cell array, after the first write signal is generated, and then compares the stored data with the received bits of data to determine whether each of the received bits of data was written to the memory. In response to a second write signal, received bits of data determined not to have been written during the first write signal, are written.
摘要翻译：一种方法将数据写入电阻性存储器，如自旋扭矩传递磁随机存取存储器（STT-MRAM）。该方法响应于第一写入信号将接收到的数据位写入存储单元阵列。该方法还在生成第一写信号之后从存储单元阵列中读取存储的数据，然后将所存储的数据与接收的数据位进行比较，以确定每个接收的数据位是否被写入存储器。响应于第二写入信号，写入在第一写入信号期间被确定为不被写入的数据的接收位。

4. 发明申请

WO2012021775A2 SYSTEM AND METHOD TO INITIATE A HOUSEKEEPING OPERATION AT A MOBILE DEVICE 审中-公开
标题翻译：在移动设备上启动家庭操作的系统和方法
公开(公告)号：WO2012021775A2
公开(公告)日：2012-02-16
申请号：PCT/US2011/047535
申请日：2011-08-12
申请人： QUALCOMM INCORPORATED , TOMS, Thomas R. , RAO, Hari M. , KANG, Seung H. , KIM, Jung Pill , SUH, Jungwon
发明人： TOMS, Thomas R. , RAO, Hari M. , KANG, Seung H. , KIM, Jung Pill , SUH, Jungwon
IPC分类号： G11C16/30 , G11C5/14 , H04W52/00
CPC分类号： G11C16/3418 , G06F1/263 , G06F11/1048
摘要： A system and method to initiate a housekeeping operation at a mobile device is disclosed. In a particular embodiment, a method at a mobile device includes modifying a scheduled housekeeping operation in response to determining that the mobile device is in a charging mode.
摘要翻译：公开了一种在移动设备处启动内务操作的系统和方法。在特定实施例中，移动设备处的方法包括响应于确定移动设备处于充电模式而修改预定的内务操作。

5. 发明申请

WO2005040951A1 VOLTAGE TRIMMING CIRCUIT 审中-公开
标题翻译：电压调整电路
公开(公告)号：WO2005040951A1
公开(公告)日：2005-05-06
申请号：PCT/EP2004/011173
申请日：2004-10-06
申请人： INFINEON TECHNOLOGIES AG , KIM, Jung Pill , SUH, Jungwon
发明人： KIM, Jung Pill , SUH, Jungwon
IPC分类号： G05F1/10
CPC分类号： G11C29/021 , G11C5/147 , G11C29/02 , G11C29/028
摘要： Methods and circuits for minimizing or eliminating the effect of trimming circuits in a voltage generating circuit are provided. In general, the effects of channel resistance of switches of the trimming circuit are reduced by utilizing switches in series with the output, rather than in parallel with resistors, as in conventional trimming circuits. Because the switches are not in parallel with the resistors, when the switches are turned on, no channel resistance is added to the effective resistance controlled by the trimming circuit.
摘要翻译：提供了用于最小化或消除电压产生电路中的微调电路的影响的方法和电路。通常，通过利用与输出串联的开关，而不是与传统的微调电路中的电阻并联，减小了微调电路的开关的沟道电阻的影响。由于开关不与电阻并联，因此当开关导通时，由修整电路控制的有效电阻不会增加通道电阻。

6. 发明申请

WO2012149569A1 SELF-BODY BIASING SENSING CIRCUIT FOR RESISTANCE-BASED MEMORIES 审中-公开
标题翻译：用于基于电阻的存储器的自身偏心感测电路
公开(公告)号：WO2012149569A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/035882
申请日：2012-04-30
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KIM, Jisu , JUNG, Youngdon , KIM, Jung Pill , KANG, Seung H.
发明人： JUNG, Seong-Ook , KIM, Jisu , JUNG, Youngdon , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16 , G11C7/14 , G11C7/06 , G11C16/28 , G11C16/26 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/14 , G11C11/16 , G11C13/004 , G11C16/26 , G11C16/28
摘要： A resistance based memory sensing circuit (302) has reference current transistors (310, 312) feeding a reference node (204) and a read current transistor (308) feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
摘要翻译：基于电阻的存储器感测电路（302）具有馈送参考节点（204）的参考电流晶体管（310,312）和馈送感测节点的读取电流晶体管（308），每个晶体管具有在正常衬底电压下的衬底主体待机模式并且在感测模式期间偏置在比正常衬底电压低的体偏置电压。在一个选项中，体偏置电压由参考节点上的参考电压确定。处于规则衬底电压的衬底体使晶体管具有规则的阈值电压，并且在体偏置电压下的衬底体使晶体管具有低于常规阈值电压的感测模式阈值电压。

7. 发明申请

WO2012100255A1 READ SENSING CIRCUIT AND METHOD WITH EQUALIZATION TIMING 审中-公开
标题翻译：阅读感应电路和均衡时序方法
公开(公告)号：WO2012100255A1
公开(公告)日：2012-07-26
申请号：PCT/US2012/022239
申请日：2012-01-23
申请人： QUALCOMM INCORPORATED , KIM, Jung Pill , KIM, Tae Hyun
发明人： KIM, Jung Pill , KIM, Tae Hyun
IPC分类号： G11C11/16
CPC分类号： G11C7/08 , G11C11/1673
摘要： A Magnetic Random Access Memory (MRAM) includes read sensing circuitry having an equalizer device configured between a bit cell output node and a reference node of the bit cell. The equalizer is turned on to couple the output node to the reference node during an initial portion of a read operation and to decouple the output node from the reference node after an equalization delay period. A sense amplifier is enabled to provide a data output from the bit cell only after the delay period and decoupling of the output node from the reference node to provide balanced sensing speed of data represented by parallel and antiparallel state magnetic tunnel junctions (MTJs).
摘要翻译：磁性随机存取存储器（MRAM）包括具有配置在比特单元输出节点和比特单元的参考节点之间的均衡器装置的读取感测电路。在读操作的初始部分期间，均衡器被导通以将输出节点耦合到参考节点，并且在均衡延迟周期之后将输出节点与参考节点去耦。读出放大器能够仅在延迟周期之后从位单元提供数据输出，并且将输出节点与参考节点解耦，以提供由并行和反并联状态磁隧道结（MTJ）表示的数据的平衡感测速度。

8. 发明申请

WO2012009589A1 PROGRAMMABLE WRITE DRIVER FOR STT-MRAM 审中-公开
标题翻译：适用于STT-MRAM的可编程驱动程序
公开(公告)号：WO2012009589A1
公开(公告)日：2012-01-19
申请号：PCT/US2011/044094
申请日：2011-07-15
申请人： QUALCOMM INCORPORATED , RAO, Hari M. , KIM, Jung Pill , LEE, Kangho
发明人： RAO, Hari M. , KIM, Jung Pill , LEE, Kangho
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C2029/5006 , H01L27/228
摘要： A non-volatile memory structure comprises programmable write drivers for controlling drive strengths of write operations to storage elements. The memory structure comprises a storage element coupled to a bit line, a switching element coupled to the storage element, a source line and a word line, wherein the switching element is configured to change a logic state of the storage element. A first and a second write driver with programmable drive strengths are coupled to the bit line and source line respectively to enable control of drive strengths of write operations to the storage element.
摘要翻译：非易失性存储器结构包括用于控制对存储元件的写入操作的驱动强度的可编程写入驱动器。存储器结构包括耦合到位线的存储元件，耦合到存储元件的开关元件，源极线和字线，其中开关元件被配置为改变存储元件的逻辑状态。具有可编程驱动强度的第一和第二写入驱动器分别耦合到位线和源极线，以便能够控制对存储元件的写入操作的驱动强度。

9. 发明申请

WO2011119641A1 MULTIPLE INSTRUCTION STREAMS MEMORY SYSTEM 审中-公开
标题翻译：多指令流记忆系统
公开(公告)号：WO2011119641A1
公开(公告)日：2011-09-29
申请号：PCT/US2011/029477
申请日：2011-03-22
申请人： QUALCOMM Incorporated , RAO, Hari M. , KIM, Jung Pill , HAGHIGHI, Siamack
发明人： RAO, Hari M. , KIM, Jung Pill , HAGHIGHI, Siamack
IPC分类号： G11C8/08 , G11C8/16 , G11C11/16 , G11C13/00
CPC分类号： G11C11/16 , G11C8/08 , G11C8/16 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C13/0028 , G11C2213/74 , G11C2213/79
摘要： A system comprising a processor processing two threads, a memory device in communication with the processor, the memory device receiving an input address signal and comprising a plurality of groups of memory cells, each group of memory cells including two non-volatile memory cells having a same input address, each memory cell including a resistive memory element and associated with a corresponding thread.
摘要翻译：一种系统，包括处理两个线程的处理器，与所述处理器通信的存储器设备，所述存储器设备接收输入地址信号并且包括多组存储器单元，每组存储器单元包括两个非易失性存储单元，相同的输入地址，每个存储单元包括电阻性存储器元件并与相应的线程相关联。

10. 发明申请

WO2012116375A1 MAGNETIC RANDOM ACCESS MEMORY (MRAM) READ WITH REDUCED DISTURB FAILURE 审中-公开
标题翻译：磁性随机存取存储器（MRAM）读取与减少的干扰故障
公开(公告)号：WO2012116375A1
公开(公告)日：2012-08-30
申请号：PCT/US2012/026831
申请日：2012-02-27
申请人： QUALCOMM INCORPORATED , KIM, Jung Pill , KIM, Tae Hyun , LEE, Kangho
发明人： KIM, Jung Pill , KIM, Tae Hyun , LEE, Kangho
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/1693
摘要： Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ.
摘要翻译：磁流体随机存取存储器（MRAM）中的磁隧道结（MTJ）在经过MTJ的电流导致由于自旋转移转矩（STT）从平行状态到抗反射的MTJ自发切换时，受到读取干扰事件，平行状态或从反平行状态到并行状态。因为MTJ的状态对应于存储的数据，读取干扰事件可能导致MRAM设备中的数据丢失。通过控制通过MTJ的电流的方向可以减少读取干扰事件。例如，可以基于参考MTJ的状态来选择通过参考MTJ的当前方向。在另一示例中，可以交替通过数据或参考MTJ的当前方向，使得MTJ仅在MTJ上的大约一半的读取操作期间经受读取干扰事件。

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