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    • 6. 发明申请
    • THREE-PHASE GSHE-MTJ NON-VOLATILE FLIP-FLOP
    • 三相GSHE-MTJ非挥发性FLIP-FLOP
    • WO2015116416A1
    • 2015-08-06
    • PCT/US2015/011899
    • 2015-01-19
    • QUALCOMM INCORPORATED
    • WU, WenqingYUEN, Kendrick Hoy LeongARABI, Karim
    • H03K3/3562G11C11/16G11C11/18
    • G11C11/1693G11C11/155G11C11/16G11C11/161G11C11/1659G11C11/1673G11C11/1675G11C11/18G11C14/0081H03K3/356008H03K3/35625H03K3/45
    • Systems and methods are directed to a three-phase non-volatile flip- flop (NVFF) (500), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure (Jl, J2), with a first GSHE-MTJ (Jl) and a second GSHE-MTJ (J2) coupled between a first combined terminal (Al, B2) and a second combined terminal (Bl, A2), and a slave stage (Invl, Inv2, EQ) formed from a first inverter cross-coupled with a second inverter. A first data value (d) is read out from the slave stage during a read phase (Phi2= 1) of the same clock cycle that a second data value (d) is written into the master stage during a write phase (Phi3= 1). The three-phase NVFF includes three control signals (Phi 1, 2, 3), for controlling an initialization phase (Phil= 1) of the slave stage, the read phase (Phi2= 1), and the write phase (Phi3= 1).
    • 系统和方法涉及三相非易失性触发器(NVFF)(500),其包括由双巨型自旋霍尔效应(GSHE) - 磁性隧道结(MTJ)结构(Jl, 具有耦合在第一组合终端(A1,B2)和第二组合终端(B1,A2)之间的第一GSHE-MTJ(J1)和第二GSHE-MTJ(J2)和从属级(Inv1, Inv2,EQ)由与第二反相器交叉耦合的第一反相器形成。 在写入阶段期间将第二数据值(d)写入主级的相同时钟周期的读取阶段(Phi2 = 1)期间从第一数据值(d)读出第一数据值(d)(Phi3 = 1 )。 三相NVFF包括用于控制从站的初始化阶段(Phil = 1),读取相位(Phi2 = 1)和写入阶段(Phi3 = 1)的三个控制信号(Phi 1,2,3) )。
    • 7. 发明申请
    • MULTI-LEVEL CELL DESIGNS FOR HIGH DENSITY LOW POWER GSHE-STT MRAM
    • 用于高密度低功率GSHE-STT MRAM的多级电池设计
    • WO2015116415A1
    • 2015-08-06
    • PCT/US2015/011898
    • 2015-01-19
    • QUALCOMM INCORPORATED
    • WU, WenqingYUEN, Kendrick Hoy LeongARABI, Karim
    • G11C11/18G11C11/56
    • G11C11/1675G11C11/16G11C11/161G11C11/1659G11C11/1673G11C11/18G11C11/5607H01L43/14
    • Systems and methods are directed to multi-level cell (MLC) comprising: two or more programmable elements coupled to a common access transistor, wherein each one of the two or more programmable elements has a corresponding unique set of two or more switching resistances and two or more switching currents characteristics, such that combinations of the two or more programmable elements configured in the respective two or more switching resistance correspond to multi-bit binary states controllable by passing switching currents through the common access transistor. Each one of the two or more programmable elements includes one or more hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) cell, with two or more hybrid GSHE-STT MRAM cells coupled in parallel.
    • 系统和方法涉及多级单元(MLC),其包括:耦合到公共存取晶体管的两个或多个可编程元件,其中两个或多个可编程元件中的每一个具有两个或更多个开关电阻的对应唯一集合,以及两个 或更多的开关电流特性,使得在相应的两个或更多个开关电阻中配置的两个或多个可编程元件的组合对应于通过将开关电流通过公共存取晶体管而可控的多位二进制状态。 两个或多个可编程元件中的每一个包括一个或多个混合巨型旋转霍尔效应(GSHE) - 转移转矩(STT)磁阻随机存取存储器(MRAM)单元,其中两个或更多个并联的GSHE-STT MRAM单元并联 。