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21. 发明申请

WO2011152938A1 MEMORY DEVICE COMPRISING A JUNCTIONLESS THIN- FILM TRANSISTOR 审中-公开
标题翻译：包含无连接薄膜晶体管的存储器件
公开(公告)号：WO2011152938A1
公开(公告)日：2011-12-08
申请号：PCT/US2011/034517
申请日：2011-04-29
申请人： SANDISK TECHNOLOGIES INC. , SAMACHISA, George , ALSMEIER, Johann , MIHNEA, Andrei
发明人： SAMACHISA, George , ALSMEIER, Johann , MIHNEA, Andrei
IPC分类号： H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/112 , H01L27/12 , H01L29/788 , H01L29/792 , H01L21/77 , H01L27/115 , B82Y10/00 , G11C16/04 , H01L27/06 , H01L27/24 , H01L29/06
CPC分类号： H01L27/1214 , B82Y10/00 , G11C16/0483 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/112 , H01L27/11206 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device (200) includes at least one junctionless transistor and a storage region. The junctionless transistor is a TFT and includes a junctionless, heavily doped semiconductor channel (204) having two dimensions less that 100 nm. The memory device can be a NAND flash memory or a resistance - switching memory. The memory cells can be integrated in three dimensions.
摘要翻译：非易失性存储器件（200）包括至少一个无连接晶体管和存储区域。无连接晶体管是TFT，并且包括具有小于100nm的二维的无连接重掺杂半导体沟道（204）。存储器件可以是NAND闪存或电阻切换存储器。存储单元可以集成在三维中。

22. 发明申请

WO2011050464A1 TWIN WELL SPLIT-CHANNEL OTP MEMORY CELL 审中-公开
标题翻译：双通道分支通道OTP存储单元
公开(公告)号：WO2011050464A1
公开(公告)日：2011-05-05
申请号：PCT/CA2010/001700
申请日：2010-10-29
申请人： SIDENSE CORP. , KURJANOWICZ, Wlodek
发明人： KURJANOWICZ, Wlodek
IPC分类号： G11C17/08 , G11C17/14
CPC分类号： G11C17/16 , H01L27/112 , H01L27/11206
摘要： A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116, are formed in twin wells 102 & 104. The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104. The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.
摘要翻译：具有双阱的一次性可编程存储单元，以在减少电流泄漏的同时改善电介质击穿。存储单元使用用于核心和I / O（输入/输出）电路的标准CMOS工艺制造。具有存取晶体管和反熔丝器件的双晶体管存储单元或具有双厚度栅极氧化物114和116的单晶体管存储单元100形成在双阱102和104中。双阱的类型与彼此可以是N型阱102，而另一个可以是P型阱104.抗熔丝器件由薄栅极氧化物形成，并且与用于核心电路的阱类似。存取晶体管形成有厚栅极氧化物，并且与用于I / O电路的阱类似。

23. 发明申请

WO2010147029A1 半導体デバイス审中-公开
标题翻译：半导体器件
公开(公告)号：WO2010147029A1
公开(公告)日：2010-12-23
申请号：PCT/JP2010/059704
申请日：2010-06-08
申请人：ソニー株式会社 , 鳥毛裕二
发明人：鳥毛　裕二
IPC分类号： G11C17/14 , G11C13/00 , H01L21/8246 , H01L27/10 , H01L27/105
CPC分类号： G11C17/16 , G11C13/0004 , G11C13/003 , G11C17/18 , G11C2213/74 , G11C2213/79 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11286
摘要：　アクセスタイムの短縮や消費電力の低減と、ワード線１本当たりの記憶ビット数の向上を両立させる。メモリセルアレイ１は、流れる電流に応じて抵抗値が変化するフューズ素子Ｆと、フューズ素子Ｆに対し並列接続された複数のセルトランジスタ（ＴＲＢ１,ＴＲＢ２）とをもつメモリセルＭＣを少なくとも１ライン分配置した構成を有する。当該半導体デバイスは、複数のセルトランジスタ（ＴＲＢ１,ＴＲＢ２）のうち、オンするセルトランジスタの数が、外部から入力される書き込み制御信号（ＷＲＩＴＥ）と内部のロジック回路５（およびワード線駆動回路４）により制御可能である。
摘要翻译：公开了一种半导体器件，其中可以平衡访问时间或功耗的减少以及每个字线的存储器位数的改善。存储单元阵列（1）具有这样的结构，其中存储单元（MC）包括熔丝元件（F），其电阻值根据流动电流而变化，并且多个单元晶体管（TRB1，TRB2）连接与熔丝元件（F）并联，由至少一行的价值排列。在半导体装置中，可以通过从外部输入的写入控制信号（WRITE）来控制多个单元晶体管（TRB1，TRB2）中导通的单元晶体管的数量，以及逻辑电路（5）（和字线驱动电路（4））。

24. 发明申请

WO2008080213A1 HIGH SPEED OTP SENSING SCHEME 审中-公开
标题翻译：高速OTP感应方案
公开(公告)号：WO2008080213A1
公开(公告)日：2008-07-10
申请号：PCT/CA2007/000503
申请日：2007-03-29
申请人： SIDENSE CORP. , KURJANOWICZ, Wlodek , SMITH, Steven
发明人： KURJANOWICZ, Wlodek , SMITH, Steven
IPC分类号： G11C17/18 , G11C17/08 , G11C17/16
CPC分类号： G11C17/16 , G11C17/18 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
摘要翻译：公开了一种用于非易失性存储器阵列的高速感测方案。存储器阵列包括以互补位线配置布置的非易失性存储器单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路和位线用于感测互补位线对之间的电压差的读出放大器。当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

25. 发明申请

WO2008059940A1 MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：记忆元件及其制造方法和半导体器件
公开(公告)号：WO2008059940A1
公开(公告)日：2008-05-22
申请号：PCT/JP2007/072232
申请日：2007-11-08
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , YOSHIZUMI, Kensuke
发明人： YOSHIZUMI, Kensuke
IPC分类号： H01L27/10 , H01L27/28 , H01L51/05
CPC分类号： H01L27/1214 , B82Y10/00 , G11C13/00 , G11C13/0014 , G11C2213/77 , G11C2213/79 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L27/12 , H01L27/1203 , H01L45/145 , Y10S977/773
摘要： The memory element has a structure at least including a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer. The memory layer is formed by a droplet discharge method using nanoparticles of a conductive material each of which is coated with an organic thin film. Specifically, a composition in which nanoparticles of a conductive material each of which is coated with an organic thin film are dispersed in a solvent is discharged (ejected) as ink droplets, and the solvent is dried to be vaporized to form the memory layer. Accordingly, a memory element can be formed simply. In addition, efficiency in the use of materials can be improved and yield is also improved, so that the memory element can be provided at low cost.
摘要翻译：存储元件具有至少包括第一导电层，第二导电层和设置在第一导电层和第二导电层之间的存储层的结构。存储层通过使用导电材料的纳米颗粒的液滴喷射法形成，每个导电材料都涂覆有机薄膜。具体而言，将涂布了有机薄膜的导电性材料的纳米粒子分散在溶剂中的组合物以墨滴的形式排出（喷射），将溶剂干燥而蒸发形成记忆层。因此，可以简单地形成存储元件。此外，可以提高材料使用的效率，并且提高产量，从而可以以低成本提供存储元件。

26. 发明申请

WO2008050880A1 SEMICONDUCTOR DEVICE INCLUDING STORAGE DEVICE AND METHOD FOR DRIVING THE SAME 审中-公开
标题翻译：包括存储器件的半导体器件及其驱动方法
公开(公告)号：WO2008050880A1
公开(公告)日：2008-05-02
申请号：PCT/JP2007/070969
申请日：2007-10-22
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , TOKUNAGA, Hajime , SAITO, Toshihiko
发明人： TOKUNAGA, Hajime , SAITO, Toshihiko
IPC分类号： H01L27/10
CPC分类号： H01L27/112 , G11C17/16 , H01L21/84 , H01L27/105 , H01L27/11206 , H01L27/11286 , H01L27/12
摘要： A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials.
摘要翻译：提出了可以使用相同的写入和读取电压值来操作使用硅化物反应的存储元件的存储装置的结构及其驱动方法。本发明涉及一种包括存储元件和电路的存储装置，该电路改变向用于写入（或写入）的不同极性的写入（或读取）存储元件的电压施加电压的极性。存储元件至少包括第一导电层，在第一导电层上形成的包括硅的膜，以及形成在硅膜上的第二导电层。存储元件的第一导电层和第二导电层使用不同的材料形成。

27. 发明申请

WO2008019616A1 ELECTRICAL THIN FILM MEMORY 审中-公开
标题翻译：电薄膜存储器
公开(公告)号：WO2008019616A1
公开(公告)日：2008-02-21
申请号：PCT/CN2007/070430
申请日：2007-08-08
申请人： HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO., LTD , SHUY, Geoffrey, Wen Tai , CHIU, Raymond, Ping Yiu
发明人： SHUY, Geoffrey, Wen Tai , CHIU, Raymond, Ping Yiu
IPC分类号： H01L27/10
CPC分类号： G11C17/16 , B82Y10/00 , G11C13/00 , G11C13/0014 , G11C13/0069 , G11C2013/009 , G11C2213/77 , G11C2213/79 , H01L27/101 , H01L27/1021 , H01L27/112 , H01L27/11206
摘要： A memory device (100) includes a layer of material structure (110) and a plurality of memory cells (120) each formed using a corresponding different portion of the layer. Each memory cell (120) is constructed and designed to change a material property of the corresponding portion of the layer upon application of an electrical write signal. The memory device (100) includes circuitry for outputting a signal indicating presence or absence of a change of the material property in the memory cells (120).
摘要翻译：存储器件（100）包括材料结构层（110）和多个存储单元（120），每个存储单元使用层的相应不同部分形成。每个存储单元（120）被构造和设计成在施加电写信号时改变层的对应部分的材料特性。存储器件（100）包括用于输出指示存储单元（120）中材料特性变化的有无的信号的电路。

28. 发明申请

WO2006119180A3 ONE TIME PROGRAMMABLE READ ONLY MEMORY 审中-公开
标题翻译：一次可编程只读存储器
公开(公告)号：WO2006119180A3
公开(公告)日：2007-05-31
申请号：PCT/US2006016612
申请日：2006-05-01
申请人： TEXAS INSTRUMENTS INC , WU XIAOJU
发明人： WU XIAOJU
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L27/112 , H01L27/11206
摘要： A one time programmable (OTP) transistor based electrically programmable read only memory (EPROM) cell (100) is disclosed. The cell includes multiple concentric rings (108, 110) from which gate structures are formed. An inner transistor based cell (130) formed from the inner ring is shielded from isolation material (106) by one or more outer rings. A lack of overlap between the inner transistor and isolation material promotes enhanced charge/data retention by avoiding high electric fields that may otherwise develop at such overlap regions.
摘要翻译：公开了一种基于时间可编程（OTP）晶体管的电可编程只读存储器（EPROM）单元（100）。电池包括形成栅极结构的多个同心环（108,110）。由内圈形成的内部基于晶体管的电池（130）通过一个或多个外环与隔离材料（106）屏蔽。内部晶体管和隔离材料之间缺少重叠通过避免在这种重叠区域可能发生的高电场来促进增强的电荷/数据保持。

29. 发明申请

WO2007008903A2 MEMORY CELL COMPRISING A THIN FILM THREE-TERMINAL SWITCHING DEVICE HAVING A METAL SOURCE AND/OR DRAIN REGION 审中-公开
标题翻译：包含金属源和/或排水区域的薄膜三端开关装置的存储单元
公开(公告)号：WO2007008903A2
公开(公告)日：2007-01-18
申请号：PCT/US2006/026898
申请日：2006-07-11
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
IPC分类号： H01L21/8247 , H01L27/11 , H01L27/115 , H01L27/06
CPC分类号： H01L27/1203 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L21/84 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L29/685 , H01L29/786 , H01L29/8605 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： A nonvolatile memory cell comprising a switchable resistor memory element and a thin-film three- terminal switching device, preferably a MOSFET, in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high-resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device. Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.
摘要翻译：一种非易失性存储单元，包括可切换电阻存储元件和薄膜三端开关器件，优选地是串联的MOSFET。可切换电阻存储元件具有至少两个稳定的电阻状态的特性，例如高电阻状态和低电阻状态。它在两个状态之间切换，并且通过提供通过三端开关装置的适当电流来感测其电阻状态（以及因此的小区的数据状态）。本发明的优选实施例包括高密度单片三维存储器阵列，其中这种存储器单元的多个存储器级别形成在诸如单晶硅晶片的单个衬底上方。

30. 发明申请

WO2005010934A2 THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE AND METHOD OF MAKING SAME 审中-公开
标题翻译：三维集成电路结构及其制作方法
公开(公告)号：WO2005010934A2
公开(公告)日：2005-02-03
申请号：PCT/US2004/020122
申请日：2004-06-23
申请人： LEE, Sang-Yun
IPC分类号： H01L
CPC分类号： B82Y10/00 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/10805 , H01L27/11 , H01L27/1104 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L27/11556 , H01L27/11568 , H01L27/228 , H01L27/2454 , H01L28/55 , H01L29/78642 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L29/8613 , H01L29/872
摘要： Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors. Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate. Stackable add-on layers may include interconnect lines.
摘要翻译：垂直取向的半导体器件可以添加到包括电子器件和/或互连的单独制造的衬底中。多个垂直取向的半导体器件在物理上彼此分离，并且不设置在同一半导体本体或半导体衬底内。可以将多个垂直取向的半导体器件添加到单独制造的衬底中，作为包括几个掺杂半导体区域的薄层，其在附着之后被蚀刻以产生单独的掺杂堆叠结构。或者，可以在附接到单独制造的基板之前制造多个垂直取向的半导体器件。掺杂的堆叠结构可以形成二极管，电容器，n-MOSFET，p-MOSFET，双极晶体管和浮栅晶体管的基础。铁电存储器件，铁磁存储器件，硫族化物相变器件可以形成在可堆叠的附加层中，与单独制造的衬底结合使用。可堆叠的附加层可以包括互连线。

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