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11. 发明申请

WO2011056527A2 METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 审中-公开
标题翻译：用于降低成本图案的三维矩阵阵列存储器布局方法和装置
公开(公告)号：WO2011056527A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/054013
申请日：2010-10-26
申请人： SANDISK 3D, LLC , SCHEUERLEIN, Roy E. , PETTI, Christopher J. , TANAKA, Yoichiro
发明人： SCHEUERLEIN, Roy E. , PETTI, Christopher J. , TANAKA, Yoichiro
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了用于三维存储器的存储层布局的装置，方法和系统。存储器层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储器线; 以及用于将存储器层耦合到三维存储器中的其他存储器层的多个齐触点区域。存储器线从存储器阵列块延伸并且使用侧壁限定的过程形成。存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。齐亚接触区的尺寸大约是存储器线的半间距尺寸的四倍。存储器线被布置成适合于允许单个存储器线与单个zia接触区相交并且为其他zia接触区提供其他存储器线之间的区域的图案。披露了许多其他方面。

12. 发明申请

WO2008082995A1 REVERSIBLE POLARITY DECODER CIRCUIT AND RELATED METHODS 审中-公开
标题翻译：可逆极性解码器电路及相关方法
公开(公告)号：WO2008082995A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088161
申请日：2007-12-19
申请人： SANDISK 3D LLC , YAN, Tianhong , FASOLI, Luca G. , SCHEUERLEIN, Roy E.
发明人： YAN, Tianhong , FASOLI, Luca G. , SCHEUERLEIN, Roy E.
IPC分类号： G11C11/413
CPC分类号： G11C8/08 , G11C13/00 , G11C13/0023 , G11C13/0028 , G11C2213/77
摘要： A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.
摘要翻译：公开了一种可逆极性解码器电路，其特别适用于实现多头解码器结构，例如可用于解码字线，特别是在3D存储器阵列中。解码器电路向半选择的字线驱动电路的栅极提供过驱动电压偏置，以将半选择的字线牢固地保持在非活动电平。如果存储器阵列被偏置在或接近击穿电压，则该过驱动电压可能大于解码晶体管的击穿电压。然而，在所描述的实施例中，解码器电路实现这一点，而不会对解码器电路的任一极性施加大于任何解码晶体管的击穿电压的电压。

13. 发明申请

WO2015148399A1 NON-VOLATILE 3D MEMORY WITH CELL-SELECTABLE WORD LINE DECODING 审中-公开
标题翻译：非易失性3D存储器，具有细胞选择性字线解码
公开(公告)号：WO2015148399A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022060
申请日：2015-03-23
申请人： SANDISK 3D LLC
发明人： YAN, Tianhong , SCHEUERLEIN, Roy E.
IPC分类号： H01L27/24
CPC分类号： G11C13/0021 , G11C5/025 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L27/249
摘要： A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line (WL) in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines (331, 332) through the multiple layers of planes. The pillar lines are of a first type (331) that act as local bit lines and a second type (332) that provide access to the word lines by having respective memory elements (348) preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.
摘要翻译：存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。存储器元件各自可以通过平面中的字线（WL）和本地位线来访问。三维阵列包括穿过多层平面的柱线（331,332）的二维阵列。柱线是用作局部位线的第一类型（331）和第二类型（332），其通过将各自的存储元件（348）预设为永久低电阻状态来提供对字线的访问，用于专用于相应字线的支柱线。衬底上的金属线阵列可切换地连接到垂直位线以提供对局部位线和字线的访问。

14. 发明申请

WO2015038557A1 FET LOW CURRENT 3D RRAM NON-VOLATILE STORAGE 审中-公开
标题翻译： FET低电流3D RRAM非易失性存储
公开(公告)号：WO2015038557A1
公开(公告)日：2015-03-19
申请号：PCT/US2014/054864
申请日：2014-09-09
申请人： SANDISK 3D LLC
发明人： BANDYOPADHYAY, Abhijit , SCHEUERLEIN, Roy E. , GORLA, Chandrasekhar R. , LE, Brian
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0059 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/148
摘要： Non-volatile storage devices having reversible resistance storage elements are disclosed herein. In one aspect, a memory cell unit includes one or more memory cells and a transistor (e.g., FET) that is used to control (e.g., limit) current of the memory cells. The drain of the transistor may be connected to a first end of the memory cell. If the memory cell unit has multiple memory cells then the drain may be connected to a node that is common to a first end of each of the memory cells. The source of the transistor is connected to a common source line. The gate of the transistor may be connected to a word line. The same word line may connect to the transistor gate of several (or many) different memory cell units. A second end of the memory cell is connected to a bit line.
摘要翻译：本文公开了具有可逆电阻存储元件的非易失性存储装置。在一个方面，存储单元单元包括一个或多个存储器单元和用于控制（例如，限制）存储器单元的电流的晶体管（例如，FET）。晶体管的漏极可以连接到存储器单元的第一端。如果存储单元单元具有多个存储器单元，则漏极可以连接到每个存储器单元的第一端公用的节点。晶体管的源极连接到公共源极线。晶体管的栅极可以连接到字线。相同的字线可以连接到几个（或许多）不同存储单元单元的晶体管栅极。存储单元的第二端连接到位线。

15. 发明申请

WO2013188172A1 3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF 审中-公开
标题翻译：具有垂直位线和立柱字线和垂直开关的3D存储器及其方法
公开(公告)号：WO2013188172A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/044079
申请日：2013-06-04
申请人： SANDISK 3D LLC
发明人： SCHEUERLEIN, Roy E. , CERNEA, Raul-Adrian
IPC分类号： G11C7/18 , G11C13/00
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.
摘要翻译：具有垂直局部位线的3D存储器全局位线具有形成为垂直结构的薄膜晶体管（TFT）形式的在线垂直开关，以将局部位线切换到全局位线。 TFT被实现为通过强耦合的选择栅极来切换由局部位线承载的最大电流，该选择栅极必须装配在局部位线周围的空间内。选择栅极的最大厚度是通过选择栅极实现的，该选择栅极从局部位线的两侧专门占据x方向的空间。该行的奇数和偶数位线的开关在z方向上交错和偏移，使得偶数和奇数局部位线的选择栅极沿x方向不重合。通过环绕选择门进一步增强切换。

16. 发明申请

WO2008082994A1 MULTIPLE POLARITY REVERSIBLE CHARGE PUMP CIRCUIT AND RELATED METHODS 审中-公开
标题翻译：多极性反相充电泵电路及相关方法
公开(公告)号：WO2008082994A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088159
申请日：2007-12-19
申请人： SANDISK 3D LLC , AL-SHAMMA, Ali , SCHEUERLEIN, Roy E.
发明人： AL-SHAMMA, Ali , SCHEUERLEIN, Roy E.
IPC分类号： H03L7/093
CPC分类号： H02M3/073 , G11C5/145 , G11C13/0038 , G11C2213/77 , H02M2003/071
摘要： A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.
摘要翻译：公开了一种多极性可逆电荷泵电路，其在某些实施例中可被配置为有时产生正电压并且可以反向以在其它时间产生负电压。如果不同时需要正电压和负电压，则这种电荷泵电路是有利的。在某些其他实施例中，电荷泵电路仅在一种工作模式下产生仅仅正升压电压的高输出电流，而在另一种工作模式下产生较低电流正和负升压电压输出。公开了某些可擦除存储器阵列技术的使用，特别是某些电阻性无源元件存储单元，更具体地在三维存储器阵列中使用。

17. 发明申请

WO2008016932A3 METHOD AND APPARATUS FOR PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 审中-公开
公开(公告)号：WO2008016932A3
公开(公告)日：2008-02-07
申请号：PCT/US2007/074883
申请日：2007-07-31
申请人： SANDISK 3D LLC , FASOLI, Luca G. , PETTI, Christopher J. , SCHEUERLEIN, Roy E.
发明人： FASOLI, Luca G. , PETTI, Christopher J. , SCHEUERLEIN, Roy E.
IPC分类号： G11C11/00
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

18. 发明申请

WO2007008699A3 APPARATUS AND METHOD FOR READING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS 审中-公开
公开(公告)号：WO2007008699A3
公开(公告)日：2007-01-18
申请号：PCT/US2006/026579
申请日：2006-07-10
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy E.
发明人： SCHEUERLEIN, Roy E.
IPC分类号： G11C11/00 , G11C7/00
摘要： A non volatile memory cell (220) includes a svvitchable resistor memory element (222) in series with a switch device (224). an array of such cells (220) may be programmed using only positive voltages. A method for programming such cells (220) also support a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supply. A method reading such cells (220) reduces read disturb of a selected memory cell (220) by impressing a read bias voltage (BIAS) having a olarity opposite that of a set voltage employed to change the switchable resistor memory element (222) to a low resistance state.

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