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11. 发明申请

WO2008016421A3 MIXED-USE MEMORY ARRAY WITH DIFFERENT DATA STATES AND METHOD FOR USE THEREWITH 审中-公开
标题翻译：具有不同数据状态的混合使用存储器阵列及其使用方法
公开(公告)号：WO2008016421A3
公开(公告)日：2008-05-02
申请号：PCT/US2007013772
申请日：2007-06-12
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
IPC分类号： G11C11/56 , G11C13/02
CPC分类号： G11C17/165 , G11C11/56 , G11C11/5692 , G11C13/0002 , G11C17/16 , G11C29/76 , G11C2211/5641 , G11C2211/5646 , G11C2213/72
摘要： A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X?Y.
摘要翻译：公开了具有不同数据状态的混合使用存储器阵列及其使用方法。在一个优选实施例中，提供了包括多个存储器单元的存储器阵列，每个存储器单元包括存储器元件，存储器元件包括可配置为至少三个电阻率状态中的一个的可切换电阻材料。第一组存储器单元使用X电阻率状态来表示X个相应的数据状态，并且第二组存储器单元使用Y电阻率状态来表示Y个相应的数据状态，其中X≥Y。

12. 发明申请

WO2008016932A2 METHOD AND APPARATUS FOR PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 审中-公开
标题翻译：包含可逆极性字线和位线解码器的被动元件存储器阵列的方法和设备
公开(公告)号：WO2008016932A2
公开(公告)日：2008-02-07
申请号：PCT/US2007074883
申请日：2007-07-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程和在一些实施例中的可重写无源元件存储器单元的示例性存储器阵列的电路和方法，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。另外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择选定阵列块内的一个或多个字线和位线，用于向选定阵列块内的选定存储器单元传送数据信息并且用于将未选择的偏置条件传送给未选择的阵列块。

13. 发明申请

WO2008016835A1 HIGH BANDWIDTH ONE TIME FIELD-PROGRAMMABLE MEMORY 审中-公开
标题翻译：高带宽一次性可编程存储器
公开(公告)号：WO2008016835A1
公开(公告)日：2008-02-07
申请号：PCT/US2007/074520
申请日：2007-07-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： H01L27/101 , G11C11/5692 , G11C17/14 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/148
摘要： A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.
摘要翻译：公开了具有相关制造和编程技术的一次性现场可编程（OTP）存储单元。根据一个实施例的OTP存储器单元包括与转向元件串联的至少一个电阻变化元件。使用反向偏置操作来对存储单元进行现场编程，该反向偏压操作可以减少通过阵列的漏电流，以及降低驱动电路在程序运行中通常产生的电压电平。可以通过在制造过程中将存储器单元从其初始状态切换到第二电阻状态来制造存储器单元阵列。在一个实施例中，出厂切换操作可以包括弹出每个存储单元的反熔丝以使它们成为第二电阻状态。将第二电阻状态的存储单元的阵列提供给终端用户。控制电路还具有存储器阵列，其可以将所选择的单元的电阻切换回其初始电阻状态，以根据从用户或主机设备接收的数据对阵列进行编程。

14. 发明申请

WO2007008902A3 NONVOLATILE MEMORY CELL COMPRISING SWITCHABLE RESISTOR AND TRANSISTOR 审中-公开
标题翻译：包含可切换电阻器和晶体管的非易失性存储器单元
公开(公告)号：WO2007008902A3
公开(公告)日：2007-09-07
申请号：PCT/US2006026897
申请日：2006-07-11
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： H01L27/24
CPC分类号： H01L45/1233 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/33 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A rewriteable nonvolatile memory cell is taught comprising a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. In preferred embodiments the memory cell is formed in an array, preferably a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. In preferred embodiments a thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. Preferably a select line extending perpendicular to the data line and reference line controls the transistor.
摘要翻译：教导了一种可重写的非易失性存储器单元，其包括串联的薄膜晶体管和可切换电阻器存储器元件。当受到在第一方向上施加的设定电压大小时，可切换电阻器元件降低电阻，并且在受到在与第一方向相反的第二方向上施加的复位电压大小时增加电阻。在优选实施例中，存储器单元形成为阵列，优选为单片三维存储器阵列，其中多个存储器级形成在单个衬底上方。在优选实施例中，薄膜晶体管和可切换电阻器存储元件电气地设置在数据线和平行的参考线之间。优选地，垂直于数据线和参考线延伸的选择线控制晶体管。

15. 发明申请

WO2006121529A3 METHOD AND APPARATUS FOR INCORPORATING BLOCK REDUNDANCY IN A MEMORY ARRAY 审中-公开
标题翻译：在存储阵列中加入块冗余的方法和装置
公开(公告)号：WO2006121529A3
公开(公告)日：2007-08-02
申请号：PCT/US2006012107
申请日：2006-03-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , SCHEUERLEIN ROY E
IPC分类号： G11C16/04
CPC分类号： G11C29/808 , G11C29/76 , G11C29/804 , G11C29/816
摘要： An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.
摘要翻译：集成电路存储器阵列包括交替的第一和第二类型的存储块，每个存储块包括与相邻存储器块中的相应阵列线共享的相应阵列线。一种类型的缺陷块的阵列线被映射到相同类型的备用块。与缺陷块的阵列线共享的第一相邻块的阵列线和与缺陷块的阵列线共享的第二相邻块的阵列线被映射到另一种类型的第二备用块从而将缺陷块和两个相邻块的部分映射到仅两个备用块中。

16. 发明申请

WO2006130801A3 TFT CHARGE STORAGE MEMORY CELL HAVING HIGH-MOBILITY CORRUGATED CHANNEL AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有高移动性修正通道的TFT充电存储单元及其制造方法
公开(公告)号：WO2006130801A3
公开(公告)日：2007-04-12
申请号：PCT/US2006021373
申请日：2006-06-01
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： H01L21/336 , G11C16/04 , H01L21/8247 , H01L21/84 , H01L27/06 , H01L27/115 , H01L27/12 , H01L29/06 , H01L29/10 , H01L29/786 , H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , G11C16/0475 , H01L21/845 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1211 , H01L29/0649 , H01L29/1037 , H01L29/66833 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/78618 , H01L29/7881 , H01L29/792
摘要： A rewriteable nonvolatile memory cell having two. bits. per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive na®ocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing- additional isolation between the two storage regions. The channel region is deposited and is preferably formed of polycrystalline germanium or silicon-germanium. The memory cell of the present invention can be formed in memory arrays; in preferred embodiments,, multiple memory levels are formed stacked above a single substrate. The memory cell comprises a transistor (50) having source (52) and drain (54) connected to bit lines (30). The channel region is formed over a dielectric structure (32) and is covered by a charge storage dielectric (36) and a wordline (44).
摘要翻译：具有两个可重写的非易失性存储单元。位。描述每个单元。存储单元优选通过通过通道热电子注入方法将电荷存储在介电电荷存储层中或电隔离的导电非晶体中来进行操作。在优选实施例中，通道区域具有波纹形状，提供了两个存储区域之间的附加隔离。沟道区域被沉积并且优选地由多晶锗或硅 - 锗形成。本发明的存储单元可以形成在存储器阵列中; 在优选实施例中，在单个衬底上堆叠形成多个存储器级。存储单元包括具有连接到位线（30）的源极（52）和漏极（54）的晶体管（50）。沟道区形成在电介质结构（32）上并由电荷存储电介质（36）和字线（44）覆盖。

17. 发明申请

WO2007008902A2 NONVOLATILE MEMORY CELL COMPRISING SWITCHABLE RESISTOR AND TRANSISTOR 审中-公开
标题翻译：非易失性存储器单元包含可切换电阻和晶体管
公开(公告)号：WO2007008902A2
公开(公告)日：2007-01-18
申请号：PCT/US2006/026897
申请日：2006-07-11
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： H01L27/24
CPC分类号： H01L45/1233 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/33 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/085 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A rewriteable nonvolatile memory cell is taught comprising a thin film transistor and a switchable resistor memory element in series. The switchable resistor element decreases resistance when subjected to a set voltage magnitude applied in a first direction, and increases resistance when subjected to a reset voltage magnitude applied in a second direction opposite the first. In preferred embodiments the memory cell is formed in an array, preferably a monolithic three dimensional memory array in which multiple memory levels are formed above a single substrate. In preferred embodiments a thin film transistor and a switchable resistor memory element are electrically disposed between a data line and a reference line which are parallel. Preferably a select line extending perpendicular to the data line and reference line controls the transistor.
摘要翻译：教导包括薄膜晶体管和可切换电阻存储元件的可重写非易失性存储单元。当经受在第一方向施加的设定电压幅值时，可切换电阻元件降低电阻，并且当经受与第一方向相反的第二方向施加的复位电压幅值时，电阻增加。在优选实施例中，存储器单元形成为阵列，优选其中在单个衬底上方形成多个存储器级的单片三维存储器阵列。在优选实施例中，薄膜晶体管和可切换电阻器存储元件电气地布置在平行的数据线和参考线之间。优选地，垂直于数据线和参考线延伸的选择线控制晶体管。

18. 发明申请

WO2007008701A2 APPARATUS AND METHOD FOR PROGRAMMING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS 审中-公开
标题翻译：用于编程非易失性存储器单元阵列的装置和方法，包括可切换电阻器存储器元件
公开(公告)号：WO2007008701A2
公开(公告)日：2007-01-18
申请号：PCT/US2006/026581
申请日：2006-07-10
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： G11C7/10
CPC分类号： G11C13/0011 , G11C11/5614 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/79
摘要： A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supplies. A method for reading such cells reduces read disturb of a selected memory cell by impressing a read bias voltage having a polarity opposite that of a set voltage employed to change the switchable resistor memory element to a low resistance state. Such programming and read methods are well suited for use in a three-dimensional memory array formed on multiple levels above a substrate, particularly those having extremely compact array line drivers on very tight layout pitch.
摘要翻译：非易失性存储器单元包括与开关器件串联的可切换电阻器存储器元件。这种单元的阵列可以仅使用正电压来编程。用于对这样的单元进行编程的方法还支持0和1数据状态的直接写入而不需要块擦除操作，并且可用于相对低电压的电源。通过施加具有与用于将可切换电阻器存储器元件改变为低电阻状态的设定电压极性相反的读取偏置电压，用于读取这些单元的方法减少了所选存储器单元的读取干扰。这种编程和读取方法非常适合用于形成在衬底上多层上的三维存储器阵列，特别是那些在非常紧凑的布局间距上具有非常紧凑的阵列线驱动器的阵列。

19. 发明申请

WO2006105435A1 TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 审中-公开
标题翻译：用于紧凑的内存阵列的晶体管布局配置
公开(公告)号：WO2006105435A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/012039
申请日：2006-03-31
申请人： SANDISK 3D LLC , PETTI, Christopher J. , SCHEUERLEIN, Roy E. , KUMAR, Tanmay , BANDYOPADHYAY, Abhijit
发明人： PETTI, Christopher J. , SCHEUERLEIN, Roy E. , KUMAR, Tanmay , BANDYOPADHYAY, Abhijit
IPC分类号： G01J1/12
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。

20. 发明申请

WO2004090905A3 THREE-DIMENSIONAL MEMORY DEVICE INCORPORATING SEGMENTED BIT LINE MEMORY ARRAY 审中-公开
标题翻译：配有分隔线位线存储器阵列的三维存储器件
公开(公告)号：WO2004090905A3
公开(公告)日：2005-06-02
申请号：PCT/US2004009756
申请日：2004-03-31
申请人： MATRIX SEMICONDUCTOR INC , SCHEUERLEIN ROY E , ILKBAHAR ALPER , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , ILKBAHAR ALPER , FASOLI LUCA G
IPC分类号： G11C7/18 , G11C11/06 , G11C11/4097 , G11C16/04 , G11C17/12 , G11C17/18 , H01L31/0328
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0466 , G11C17/12 , G11C17/18 , G11C2213/71 , G11C2213/77 , Y10S257/91
摘要： A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line.
摘要翻译：三维（3D）高密度存储器阵列包括多个分段位线（即感测线），其中存储器阵列内的段切换器件将段连接到全局位线。分段交换设备驻留在集成电路的一个或多个层上，优选地驻留在每个位线层上。全局位线优选地位于存储器阵列下方的一个层上，但可驻留在多于一个层上。位线段优选地共享到相关联的全局位线的垂直连接。

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