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1. 发明公开

EP4239667A1 MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE 审中-实审
公开(公告)号：EP4239667A1
公开(公告)日：2023-09-06
申请号：EP22776854.6
申请日：2022-03-03
申请人： Changxin Memory Technologies, Inc.
发明人： LI, Guangji
IPC分类号： H01L21/8242 , H01L27/108
摘要： The present disclosure discloses a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method includes: providing a base, active regions arranged at intervals along a first direction being arranged in the base; forming, on the base, bit line structures arranged at intervals; forming a contact structure between two adjacent ones of the bit line structures; forming a barrier structure on the contact structure, the barrier structures being arranged in correspondence with and connected to the bit line structure, and a first recess being formed between any adjacent barrier structures; and forming a conductive structure in the first recess, the conductive structure including a protective layer and a conductive portion, and the protective layer wrapping a sidewall and a bottom wall of the conductive portion.

2. 发明公开

EP4232421A1 DIELECTRIC FILM-FORMING COMPOSITION 审中-实审
公开(公告)号：EP4232421A1
公开(公告)日：2023-08-30
申请号：EP21883561.9
申请日：2021-10-12
申请人： FUJIFILM Electronic Materials U.S.A, Inc.
发明人： DE, Binod B. , SAKAMURI, Raj , MALIK, Sanjay , DILOCKER, Stephanie , REINERTH, William A.
IPC分类号： C04B35/491 , C23C30/00 , H01L27/108

3. 发明公开

EP4220699A1 FABRICATION METHOD FOR SEMICONDUCTOR STRUCTURE 审中-实审
公开(公告)号：EP4220699A1
公开(公告)日：2023-08-02
申请号：EP21940441.5
申请日：2021-09-24
申请人： Changxin Memory Technologies, Inc.
发明人： LU, Jingwen
IPC分类号： H01L21/8242 , H01L27/108
摘要： The present disclosure provides a method of manufacturing a semiconductor structure, including: providing a base; forming first mask layers and second mask layers on the base, wherein the first mask layers each extend along a first direction, the second mask layers each extend along a second direction, the first direction is different from the second direction, and the first mask layers intersect the second mask layers; cutting off the first mask layers to form first sub-mask layers, wherein the second mask layers each span a plurality of the first sub-mask layers, and partial sidewalls of each of the first sub-mask layers are covered by the second mask layers; etching the base by using a first etching process, to form active regions; forming a isolation structure; and forming word line trench.

4. 发明公开

EP4207287A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREFOR 审中-实审
公开(公告)号：EP4207287A1
公开(公告)日：2023-07-05
申请号：EP21879030.1
申请日：2021-07-16
申请人： Changxin Memory Technologies, Inc.
发明人： WU, Ping-Heng
IPC分类号： H01L27/108 , H01L21/8242
摘要： Provided are a semiconductor device, a semiconductor structure and a forming method therefor, which relate to the technical field of semiconductors. The forming method comprises: providing a substrate and forming a sacrificial layer thereon; patterning the sacrificial layer to form trenches and through holes that are distributed side-by-side in the sacrificial layer; forming an insulating layer which covers side walls of the trenches and side walls of the through holes; sequentially forming conductive layers and passivation layers in the trenches and the through holes, so as to form bit line structures in the trenches; and removing the passivation layers located in the through holes so as to form capacitive contact structures in the through holes.

5. 发明公开

EP4195275A1 DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREFOR 审中-实审
公开(公告)号：EP4195275A1
公开(公告)日：2023-06-14
申请号：EP21868227.6
申请日：2021-07-06
申请人： Changxin Memory Technologies, Inc.
发明人： LI, Sen , WAN, Qiang , LIU, Tao , XU, Penghui
IPC分类号： H01L27/108
摘要： The present disclosure provides a Dynamic Random Access Memory (DRAM) and a manufacturing method thereof, and relates to the technical field of memories. The DRAM comprises a substrate and connection pads and capacitors disposed on the substrate. Here, the capacitor comprises a first electrode layer; the first electrode layer is provided with an extension part extending towards the substrate, and the extension part is coated on a top surface and a side surface of the connection pad. The extension part provided by the present disclosure may be coated on the top surface and the side surface of the connection pad at the same time, so that a contact area between the first electrode layer and the connection pad is increased, contact resistance between the first electrode layer and the connection pad is reduced, thus signal delay of the DRAM is reduced, and the performance of the DRAM is improved. Moreover, the extension part may also increase the acting force between a capacitive holes and the connection pads, so that the collapse risk of the capacitors in a subsequent manufacturing process is reduced.

6. 发明公开

EP4138135A1 STORAGE UNIT AND PREPARATION METHOD THEREFOR, AND MEMORY AND PREPARATION METHOD THEREFOR 审中-实审
公开(公告)号：EP4138135A1
公开(公告)日：2023-02-22
申请号：EP22743699.5
申请日：2022-02-15
申请人： Changxin Memory Technologies, Inc.
发明人： XIAO, Deyuan
IPC分类号： H01L27/108
摘要： The present disclosure provides a memory cell and a manufacturing method thereof, and a memory and a manufacturing method thereof, and relates to the technical field of semiconductors. The memory unit includes a first dielectric layer and a second dielectric layer that are stacked. A first transistor is disposed in the first dielectric layer. A second transistor is disposed in the second dielectric layer. The first dielectric layer is connected to the second dielectric layer by using a connecting wire. In the present disclosure, a parasitic capacitance in the first transistor or the second transistor is used as a memory element to replace the capacitor in the related art, such that the volume occupied by the memory cells can be reduced, to ensure that the memory cells are developed in an integration direction. In addition, the first transistor and the second transistor are both metal-oxide thin-film transistors, such that the memory can have longer retention time of charge, to improve the performance of the memory while decreasing the volume of the memory.

7. 发明公开

EP4138134A1 SEMICONDUCTOR MEMORY DEVICE 审中-实审
公开(公告)号：EP4138134A1
公开(公告)日：2023-02-22
申请号：EP22167093.8
申请日：2022-04-07
申请人： Samsung Electronics Co., Ltd.
发明人： LEE, Kiseok , KIM, Keunnam , KIM, Hui-Jung , LEE, Wonsok , CHO, Min Hee
IPC分类号： H01L27/108
摘要： A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

8. 发明公开

EP4135037A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR 审中-实审转让
公开(公告)号：EP4135037A1
公开(公告)日：2023-02-15
申请号：EP21884120.3
申请日：2021-11-02
申请人： Changxin Memory Technologies, Inc.
发明人： HAN, Qinghua
IPC分类号： H01L27/108
摘要： The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming bit lines on the base, and forming semiconductor channels on surfaces of the bit lines away from the base, the semiconductor channel including a first doped region, a channel region and a second doped region arranged sequentially; forming a first dielectric layer, the first dielectric layer surrounding sidewalls of the semiconductor channels, and a first gap being provided between parts of the first dielectric layer located on sidewalls of adjacent semiconductor channels on a same bit line; forming a second dielectric layer, the second dielectric layer filling up the first gaps, and a material of the second dielectric layer being different from a material of the first dielectric layer; removing a part of the first dielectric layer to expose sidewalls of the channel regions; forming an insulating layer, covering at least sidewall surfaces of the channel regions, and second gaps being provided between the insulating layer and the second dielectric layer; and forming word lines, the word lines filling up the second gaps.

9. 发明公开

EP4128350A1 COMPUTE NEAR MEMORY WITH BACKEND MEMORY 审中-实审
公开(公告)号：EP4128350A1
公开(公告)日：2023-02-08
申请号：EP20927767.2
申请日：2020-12-23
申请人： INTEL Corporation
发明人： SHARMA, Abhishek , SATO, Noriyuki , ATANASOV, Sarah , SUMBUL, Huseyin Ekin , CHEN, Gregory K. , KNAG, Phil , KRISHNAMURTHY, Ram , YOO, Hui Jae , LE, Van H.
IPC分类号： H01L27/108 , H01L27/12 , G11C11/4096

10. 发明公开

EP4113608A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-实审
公开(公告)号：EP4113608A1
公开(公告)日：2023-01-04
申请号：EP22164916.3
申请日：2022-03-29
申请人： Samsung Electronics Co., Ltd.
发明人： PARK, Taejin , KIM, Hui-Jung , LEE, Sangho
IPC分类号： H01L27/108
摘要： A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.

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