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1. 发明公开

EP4287256A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR 审中-实审
公开(公告)号：EP4287256A1
公开(公告)日：2023-12-06
申请号：EP21928731.5
申请日：2021-07-08
申请人： Changxin Memory Technologies, Inc.
发明人： YU, Yexiao , LIU, Zhongming , FANG, Jia , CHEN, Longyang
IPC分类号： H01L27/108
摘要： The present invention relates to a semiconductor structure and a manufacturing method therefor. The manufacturing method for a semiconductor structure comprises: providing a substrate, the substrate comprising an active region and an isolation region; forming a first trench structure on the substrate, the first trench structure passing through the active region and the isolation region; forming a bit line contact structure in the first trench structure, the upper surface of the bit line contact structure being lower than the upper surface of the substrate; forming a bit line structure on the bit line contact structure, the bit line structure being at least partially located in the first trench structure; forming a bit line protection structure on the bit line structure, the bit line protection structure covering at least the upper surface of the bit line structure, and a second trench structure being provided between every two adjacent bit line protection structures; and forming a capacitor contact structure, the capacitor contact structure comprising a first capacitor contact structure and a second capacitor contact structure, wherein the second capacitor contact structure covers the upper surface and a part of the side wall of the first capacitor contact structure.

2. 发明公开

EP4273932A1 SEMICONDUCTOR APPARATUS, ELECTRONIC DEVICE, AND FORMING METHOD FOR TRANSISTOR 审中-实审
公开(公告)号：EP4273932A1
公开(公告)日：2023-11-08
申请号：EP21929492.3
申请日：2021-03-08
申请人： Huawei Technologies Co., Ltd.
发明人： HUANG, Kailiang , JING, Weiliang , FENG, Junxiao , WANG, Zhengbo
IPC分类号： H01L27/108
摘要： Embodiments of this application provide a forming method for a semiconductor apparatus, an electronic device, and a transistor, and a forming method for a memory. The method relates to the field of memory technologies, which can improve an integration density of a memory cell. The semiconductor apparatus includes a substrate and a first transistor and a second transistor that are formed on the substrate. The second transistor is electrically connected to the first transistor, the first transistor and the second transistor are arranged along a first direction perpendicular to the substrate, and the first transistor and the second transistor each include a gate, a semiconductor layer, a first electrode, and a second electrode; and in either of the first transistor and the second transistor, the gate and the semiconductor layer are arranged along a second direction parallel to the substrate, and the first electrode and the second electrode are disposed on two sides of the semiconductor layer along the first direction and are electrically connected to the semiconductor layer respectively.

3. 发明公开

EP4252276A1 FEEDFORWARD CONTROL OF MULTI-LAYER STACKS DURING DEVICE FABRICATION 审中-实审
公开(公告)号：EP4252276A1
公开(公告)日：2023-10-04
申请号：EP21898957.2
申请日：2021-11-19
申请人： Applied Materials, Inc.
发明人： PANDA, Priyadarshi , LIAN, Lei , TEDESCHI, Leonard Michael
IPC分类号： H01L21/67 , G01B11/06 , C23C16/54 , C23C16/52 , H01L27/108 , H01L21/66

4. 发明公开

EP4218055A1 VERTICAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME 审中-实审
公开(公告)号：EP4218055A1
公开(公告)日：2023-08-02
申请号：EP21944418.9
申请日：2021-12-14
申请人： Yangtze Memory Technologies Co., Ltd.
发明人： YANG, Tao , ZHAO, DongXue , YANG, Yuancheng , LIU, Lei , ZHANG, Kun , WANG, Di , ZHOU, Wenxi , XIA, ZhiLiang , HUO, ZongLiang
IPC分类号： H01L27/108

5. 发明公开

EP4195253A1 SEMICONDUCTOR STRUCTURE FORMING METHOD AND SEMICONDUCTOR STRUCTURE 审中-实审
公开(公告)号：EP4195253A1
公开(公告)日：2023-06-14
申请号：EP21871094.5
申请日：2021-08-05
申请人： Changxin Memory Technologies, Inc.
发明人： LU, Jingwen
IPC分类号： H01L21/8242 , H01L27/108
摘要： Provided is a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes the following operations. A semiconductor substrate is provided, on which bit line structures and dielectric layers that are discretely arranged are formed, in which an extension direction of the dielectric layers is intersected with an extension direction of the bit line structures, the bit line structures and the dielectric layers jointly define discrete capacitor contact openings. First conductive layers filling the capacitor contact openings are formed, in which top surfaces of the first conductive layers are lower than top surfaces of the bit line structures. Conductive contact layers located on the top surfaces of the first conductive layers are formed, in which a thickness of a first part and/or a thickness of a second part of each conductive contact layer is greater than a thickness of a third part thereof. Discrete second conductive layers electrically connected with the conductive contact layer are formed, in which the second conductive layers are configured to adjust an arrangement mode of capacitor contact structures formed by filling the capacitor contact openings.

6. 发明公开

EP4191673A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR 审中-实审
公开(公告)号：EP4191673A1
公开(公告)日：2023-06-07
申请号：EP21912952.5
申请日：2021-06-25
申请人： Changxin Memory Technologies, Inc.
发明人： WU, Baolei , WANG, Xiaoguang
IPC分类号： H01L27/108
摘要： A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate; a first transistor, including a first channel region located in the substrate; a second transistor, including a second channel region located in the substrate, the second channel region having an area different from an area of the first channel region, and the first transistor and the second transistor having a common source or a common drain; and a memory cell, connected to the common source or the common drain.

7. 发明公开

EP4152393A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME 无效
公开(公告)号：EP4152393A1
公开(公告)日：2023-03-22
申请号：EP22748212.2
申请日：2022-02-15
申请人： Changxin Memory Technologies, Inc.
发明人： WANG, Peimeng
IPC分类号： H01L27/108
摘要： The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: forming a capacitor base, the capacitor base including a plurality of capacitor switching structures and an isolation layer located between adjacent capacitor switching structures and covering top surfaces of the capacitor switching structures; removing the isolation layer covering the top surfaces of the capacitor switching structures, and exposing the capacitor switching structures; oxidizing a surface of the capacitor base exposing the capacitor switching structures, and forming an oxide layer; and removing the oxide layer, and exposing the capacitor switching structures. The present application reduces the defects on the surface of the capacitor base and avoids the short circuits between the adjacent capacitor switching structures to improve electrical properties of the semiconductor structure.

8. 发明公开

EP4123704A2 SEMICONDUCTOR DEVICE 审中-实审
公开(公告)号：EP4123704A2
公开(公告)日：2023-01-25
申请号：EP22164909.8
申请日：2022-03-29
申请人： Samsung Electronics Co., Ltd.
发明人： KANG, Jong In , CHOI, Jun Young , HONG, Yoon Gi , KIM, Tae Hoon , YEO, Sung-Jin , HAN, Sang Yeon
IPC分类号： H01L27/108
摘要： A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region and a core region, a boundary element separation film which is placed inside the substrate, and separates the cell region and the core region, and a bit line which is placed on the cell region and the boundary element separation film and extends along a first direction, in which the boundary element separation film includes a first region and a second region, a height of an upper side of the first region of the boundary element separation film is different from a height of an upper side of the second region of the boundary element separation film, on a basis of a bottom side of the boundary element separation film, and the bit line is placed over the first region and the second region of the boundary element separation film.

9. 发明公开

EP4105975A1 INTEGRATED CIRCUIT COMPRISING MEMORY CELLS WITH AIR GAPS IN UPPER METAL LAYERS 审中-实审
公开(公告)号：EP4105975A1
公开(公告)日：2022-12-21
申请号：EP22174056.6
申请日：2022-05-18
申请人： INTEL Corporation
发明人： SHARMA, Abhishek Anil , CHEN, Albert B. , GOMES, Wilfred , HAMZAOGLU, Fatih , LAJOIE, Travis W. , LE, Van H. , NIMMAGADDA, Alekhya , RESHOTKO, Miriam R. , YOO, Hui Jae
IPC分类号： H01L21/768 , H01L27/06 , H01L27/108
摘要： An example IC device includes a frontend layer (420) and a backend layer (430) with a metallization stack. The metallization stack includes a backend memory layer (432) with a plurality of memory cells (520) with backend transistors, and a layer (508) with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps (434) between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

10. 发明公开

EP4044232A1 MEMORY AND MANUFACTURING METHOD THEREFOR 审中-实审
公开(公告)号：EP4044232A1
公开(公告)日：2022-08-17
申请号：EP21773438.3
申请日：2021-06-21
申请人： Changxin Memory Technologies, Inc.
发明人： ZHAN, Kangshu , XIA, Jun , WAN, Qiang , LIU, Tao , LI, Sen
IPC分类号： H01L27/108 , H01L21/8242
摘要： Embodiments provide a memory and a fabrication method thereof, and relates to the field of storage device technology to solve the technical problem of lower storage density of the memory. The fabrication method of the memory includes: providing a substrate including a central region and an edge region connected to each other, a first contact structure electrically connected to a wordline structure in the substrate being formed in the edge region; forming a second contact structure electrically connected to the first contact structure on the edge region; forming a capacitor structure electrically connected to the wordline structure on the central region; forming a third contact structure electrically connected to the second contact structure on the second contact structure; and forming a transistor structure electrically connected to the wordline structure on the capacitor structure and the third contact structure. In this way, it is possible to increase a scope for arranging the capacitor structure, such that more capacitors can be arranged in the capacitor structure, and thus the storage density of the memory can be increased.

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