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1. 发明公开

EP2044624A1 ISOLATION STRUCTURES FOR INTEGRATED CIRCUITS AND MODULAR METHODS OF FORMING THE SAME 审中-公开
标题翻译：隔离结构用于集成电路工艺模块化教育
公开(公告)号：EP2044624A1
公开(公告)日：2009-04-08
申请号：EP07777316.6
申请日：2007-05-30
申请人： Advanced Analogic Technologies Inc.
发明人： RYU, Hyungsik , CHAN, Wai, Tien , DISNEY, Donald, Ray , WILLIAMS, Richard, K. , CHEN, Jun-wei
IPC分类号： H01L21/76
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

2. 发明公开

EP1517362A3 Verfahren zur Herstellung von Halbleiterbauelementen in einem Halbleitersubstrat 有权转让
标题翻译：一种用于在半导体衬底中制造半导体器件的过程
公开(公告)号：EP1517362A3
公开(公告)日：2007-09-05
申请号：EP04022112.9
申请日：2004-09-17
申请人： ATMEL Germany GmbH
发明人： Dietz, Franz, Dipl.-Ing. (FH) , Dudek, Volker, Dr. , Graf, Michael, Dr.
IPC分类号： H01L21/336 , H01L21/225 , H01L29/78 , H01L29/786 , H01L21/265 , H01L29/08
CPC分类号： H01L29/66659 , H01L21/2253 , H01L21/26586 , H01L21/76237 , H01L21/76283 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/7835
摘要： Vorgestellt wird ein Verfahren zur Herstellung von Halbleiterbauelementen in einem Halbleitersubstrat (12) mit den Schritten: Erzeugen von Wannen (32, 34) mit unterschiedlichem Leitfähigkeitstyp und Erzeugen von grabenförmigen Strukturen (36, 60) innerhalb des Halbleitersubstrates (12), wobei die Wannen (32, 34) durch eine Implantation und eine Eindiffusion (26, 44) von Dotierstoffen erzeugt werden, und Erzeugen und Kontaktieren von aktiven Bereichen in dem Halbleitersubstrat (12). Das Verfahren zeichnet sich dadurch aus, dass die Eindiffusion (26, 44) durch wenigstens zwei Hochtemperaturschritte erfolgt, wobei wenigstens eine erste Eindiffusion (26) durch einen ersten Hochtemperaturschritt vor einem Erzeugen der grabenförmigen Strukturen (36, 60) durchgeführt wird und wobei wenigstens eine zweite Eindiffusion (44) durch einen zweiten Hochtemperaturschritt nach dem Erzeugen der grabenförmigen Strukturen (36, 60) durchgerührt wird.

3. 发明公开

EP1117133A1 SEMICONDUCTOR DEVICE AND METHOD FOR THE SAME MANUFACTURING 审中-公开
标题翻译：半导体器件和用于相同制造的方法
公开(公告)号：EP1117133A1
公开(公告)日：2001-07-18
申请号：EP00944273.2
申请日：2000-07-06
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： OHNISHI, Teruhito , ASAI, Akira , TAKAGI, Takeshi , SAITOH, Tohru , ICHIKAWA, Yo , HARA, Yoshihiro , YUKI, Koichiro , NOZAWA, Katsuya , KATAYAMA, Koji , KANZAWA, Yoshihiko
IPC分类号： H01L29/737 , H01L27/06 , H01L21/331
CPC分类号： H01L21/76237 , H01L21/8249
摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.
摘要翻译：在双极型晶体管块中，在集电极扩散层（9）上依次层叠SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）。在基层（20a）的两个边缘上，提供由多晶硅制成的基底绝缘膜（5a）和基底延伸电极（22）。基底层（20a）具有与基底绝缘膜（5a）相同厚度的周边部分和比周边部分厚的中央部分。用于CMOS模块的基础底涂绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。可以减小由作为基极层的SiGe层和基础底涂绝缘膜5a之间的热膨胀系数差异引起的应力，并且实现了高度可靠的BiCMOS器件。

4. 发明公开

EP1033751A3 Method for forming buried layers with top-side contacts and the resulting structure 审中-公开
标题翻译： Verfahren zur Herstellung vergrabener Schichten mit obenseitigen Kontakten und die resultierende Struktur
公开(公告)号：EP1033751A3
公开(公告)日：2000-12-20
申请号：EP00104220.9
申请日：2000-03-01
申请人： Blanchard, Richard A.
发明人： Blanchard, Richard A.
IPC分类号： H01L21/74
CPC分类号： H01L21/761 , H01L21/74 , H01L21/743 , H01L21/76237 , H01L21/763
摘要： A buried layer of dopant is formed in a semiconductor by etching a series of trenches, then depositing dopant at the bottom of the trenches and diffusing until the dopant from different trenches meet to form a continuous layer. Depending on the material used to fill the trenches, the buried layer can be contacted or isolated. With this method, it becomes unnecessary to grow expensive epitaxial layers.
摘要翻译：通过蚀刻一系列沟槽，然后在沟槽的底部沉积掺杂剂并扩散到来自不同沟槽的掺杂剂相遇以形成连续层，在半导体中形成掩埋的掺杂剂层。根据用于填充沟槽的材料，掩埋层可以接触或隔离。利用这种方法，不需要生长昂贵的外延层。

5. 发明公开

EP0929098A1 Process for selectively implanting dopants into the bottom of a deep trench 失效
标题翻译：工艺的掺杂剂中的深沟槽的底部侧上的选择性注入
公开(公告)号：EP0929098A1
公开(公告)日：1999-07-14
申请号：EP98830006.7
申请日：1998-01-13
申请人： STMicroelectronics S.r.l.
发明人： Nicotra, Maria Concetta , Santangelo, Antonello , Masciarelli, Daniela Anna
IPC分类号： H01L21/761 , H01L21/265 , H01L21/266
CPC分类号： H01L21/76237 , H01L21/266 , H01L21/761 , H01L21/76232
摘要： A process for selectively introducing a dopant into the bottom of a trench (13) formed in a semiconductor material layer (10) provides for depositing a barrier layer (14) by means of a process of deposition over the semiconductor material layer (10), so as to form a deposited barrier layer (14) having, over lateral walls and a bottom wall of the trench, a thickness which is lower than a nominal thickness of the deposited barrier layer (14) over a planar surface of the semiconductor material layer (10), and implanting a dopant using the deposited barrier layer (14) as an implant mask.
摘要翻译：的方法，用于选择性地将掺杂剂引入沟槽的底部（13）形成在半导体材料层（10）提供了一种通过沉积在半导体材料层的工艺来沉积阻挡层（14）（10）以便形成具有沉积的阻挡层（14），用横向壁和沟槽的底壁的厚度的所有比在半导体材料层的平坦表面所沉积的阻挡层（14）的标称厚度下（10），以及使用该沉积的阻挡层（14），以注入掩模注入的掺杂剂。

6. 发明公开

EP0647968A2 Semiconductor device comprising a plurality of element separating trenches and method of manufacturing same 失效
标题翻译：具有多个沟槽的用于分离的部件和组件的方法的半导体器件。
公开(公告)号：EP0647968A2
公开(公告)日：1995-04-12
申请号：EP94115893.3
申请日：1994-10-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ishimaru, Kazunari
IPC分类号： H01L21/76 , H01L21/74 , H01L29/06
CPC分类号： H01L29/0649 , H01L21/743 , H01L21/76237
摘要： A buried collector layer (2) is formed on a semiconductor substrate (1). An epitaxial layer (4) is formed on the buried collector layer (2). A plurality of element separating trenches (11) of roughly the same depth and filled with an insulating material are formed in the epitaxial layer (4). When these trenches are formed deep enough to penetrate the buried collector layer to the semiconductor substrate, an impurity region of conductivity the same as that of the buried collector layer is formed at a predetermined position of the semiconductor substrate and adjoining to at least one bottom portion of a plurality of the trenches. Further, when a separation layer is formed on the semiconductor substrate and adjoining to the buried collector layer to separate the semiconductor device from another adjacent semiconductor device, at least one of a plurality of trenches is formed on a boundary surface between the buried collector layer and the separation layer.
摘要翻译：掩埋集电极层（2）被形成在半导体衬底（1）上。外延层（4）形成在集电极埋层（2）上。元件分离沟槽大致相同的深度（11）和填充有绝缘材料，以形成多个在所述外延层（4）。当合成沟槽形成足够深的穿透埋入集电极层的半导体衬底，以导电性的相同象埋入集电极层在所述半导体衬底的预定位置形成的杂质区和邻接于至少一个底部的沟槽的多元性。此外，当分离层是形成在半导体基片和邻接掩埋集电极层，以与另一相邻的半导体装置的半导体装置分开，沟槽中的多个的至少一个被形成在所述埋集电极层之间的边界表面分离层。

7. 发明公开

EP0436184A3 Method of manufacturing a semiconductor device utilising an impurity segregation phenomenon 失效
标题翻译：制造破坏性分离子的半导体器件的制造方法
公开(公告)号：EP0436184A3
公开(公告)日：1993-09-08
申请号：EP90124819.5
申请日：1990-12-19
申请人： FUJITSU LIMITED
发明人： Miura, Takao, c/o Fujitsu Limited Patent Dept.
IPC分类号： H01L21/225 , H01L21/28
CPC分类号： H01L29/517 , H01L21/28176 , H01L21/28211 , H01L21/28273 , H01L21/3105 , H01L21/76237 , H01L29/66825
摘要： A method of manufacturing a semi conductor device, the device comprising a silicon substrate (1) and an insulation layer (2; 2b; 11; 24; 32) formed on the substrate, the method comprising:-
depositing a conductive layer (4; 21) on the insulation layer (2; 2b; 11; 24; 32), which conductive layer (4; 21) is doped with an impurity material (5);
carrying out heat treatment such that the impurity material (5) segregates and accumulates in the insulation layer (2) and fixed charges (6) are formed in the insulation layer (2; 2b; 11; 24; 32).

8. 发明授权

EP0146895B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：EP0146895B1
公开(公告)日：1992-08-19
申请号：EP84115477.6
申请日：1984-12-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Higuchi, Takayoshi c/o Patent Division
IPC分类号： H01L21/76 , H01L21/32
CPC分类号： H01L21/76237 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/76216

9. 发明授权

EP0250869B1 Semiconductor integrated circuit containing analogous and digital components 失效
标题翻译：包含模拟和数字组件的半导体集成电路
公开(公告)号：EP0250869B1
公开(公告)日：1992-05-13
申请号：EP87107683.2
申请日：1987-05-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Taguchi, Minoru c/o Patent Division
IPC分类号： H01L21/76 , H01L21/82
CPC分类号： H01L21/76237 , H01L21/763 , H01L21/8226 , H01L21/8248 , H01L21/8249 , H01L27/0203 , H01L27/0623

10. 发明授权

EP0210190B1 CONTROLLED BORON DOPING OF SILICON 失效
标题翻译：有机硅的控制硼
公开(公告)号：EP0210190B1
公开(公告)日：1991-07-24
申请号：EP86900515.7
申请日：1985-12-16
申请人： AT&T Corp.
发明人： LIN, Albert, Miin-Ron
IPC分类号： H01L21/225 , H01L21/76 , H01L29/94 , H01L29/06
CPC分类号： H01L29/945 , H01L21/2256 , H01L21/76237 , Y10S438/923
摘要： A technique for doping a silicon body (10) with boron. The surface to be doped is typically a trench sidewall, to be used as a storage capacitor or for isolation. By providing a silicon dioxide diffusion control layer, (20) and a polysilicon source layer (30) that incorporates the boron, well-controlled boron doping over a wide concentration range can be obtained. Control of the doping transfer can be obtained by the choice of ambients, either dry or steam. Furthermore, removal of the silicon dioxide and polysilicon layers following the doping process is facilitated due to the etch selectivity possible between SiO2 and Si. If desired, the layers may remain on the silicon body.

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