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1. 发明公开

EP2725606A4 HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：以集成电路为高压设备
公开(公告)号：EP2725606A4
公开(公告)日：2015-07-01
申请号：EP11846055
申请日：2011-09-12
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/06 , H01L27/092
CPC分类号： H01L27/092 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0921

2. 发明公开

EP2782130A4 HIGH-VOLTAGE-RESISTANCE SEMICONDUCTOR DEVICE 有权
标题翻译：耐高压半导体器件
公开(公告)号：EP2782130A4
公开(公告)日：2015-07-08
申请号：EP12850565
申请日：2012-11-13
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU , SUMIDA HITOSHI
IPC分类号： H01L21/8234 , H01L21/761 , H01L21/765 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/423 , H01L29/78
CPC分类号： H01L29/407 , H01L21/761 , H01L21/765 , H01L21/823481 , H01L27/088 , H01L29/063 , H01L29/0878 , H01L29/402 , H01L29/42368 , H01L29/7811 , H01L29/7816
摘要： A withstand voltage region is formed to surround a logic circuit formation region. A high-voltage MOSFET (71, 72) for level shifting is formed in part of the withstand voltage region. A p - opening region (131) is formed between a drain region of the high-voltage MOSFET (71, 72) and the logic circuit formation region. A shield layer (300) connected to the negative electrode side of a power supply connected to the logic circuit formation region is disposed on the p - opening region (131). Thus, it is possible to provide a high-voltage semiconductor device including a level shifting circuit capable of making stable operation during the switching of a high-voltage IC and with long-term reliability.

3. 发明公开

EP3010042A4 SEMICONDUCTOR DEVICE 有权
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP3010042A4
公开(公告)日：2017-01-18
申请号：EP14811117
申请日：2014-06-06
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU
IPC分类号： H01L27/08 , H01L21/336 , H01L21/764 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/07 , H01L27/12 , H01L29/06 , H01L29/739 , H01L29/78 , H01L29/861 , H01L29/868
CPC分类号： H01L29/7818 , H01L21/761 , H01L21/764 , H01L27/0629 , H01L27/0727 , H01L27/1207 , H01L29/0619 , H01L29/0649 , H01L29/1095 , H01L29/7393 , H01L29/78 , H01L29/8611 , H03K17/002
摘要： In a semiconductor device (100) including a bootstrap diode (Db) and a high voltage electric field transistor (62) on a p-type semiconductor substrate (1), a cavity (3) is formed in an n - -type buried layer (50) of the semiconductor substrate (1) to use the buried layer (50) beneath the cavity as a drain drift region of the high voltage n-channel MOSFET (62), whereby a leakage current by holes (92) that flows to the semiconductor substrate (1) side in forward biasing of the bootstrap diode (Db) can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.
摘要翻译：在p型半导体衬底（1）上包括自举二极管（Db）和高电压电场晶体管（62）的半导体器件（100）中，在n型掩埋层（50）的半导体衬底（1）的半导体衬底（50），以使用所述腔下面的掩埋层（50）作为所述高电压n沟道MOSFET（62）的漏极漂移区域，由此漏电流（92）流到可以抑制自举二极管（Db）的正向偏置的半导体衬底（1）侧，并且可以增加自举电容器C1的充电电流，并且可以抑制芯片面积的增加。

4. 发明公开

EP2779225A4 SEMICONDUCTOR DEVICE 有权
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP2779225A4
公开(公告)日：2015-06-03
申请号：EP12847671
申请日：2012-10-12
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU
IPC分类号： H01L27/04 , H01L21/765 , H01L27/06 , H01L27/092 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号： H01L29/7393 , H01L21/765 , H01L27/0922 , H01L29/0634 , H01L29/0696 , H01L29/405 , H01L29/42368 , H01L29/7395 , H01L29/7816 , H01L29/7835 , H01L29/8611
摘要： An n - type region (101) encloses an n-type well region (201) in which is disposed a high-side drive circuit (300). A high resistance polysilicon thin film (401) configuring a resistive field plate structure of a high breakdown voltage junction termination region is disposed in spiral form on the n - type region (101). Also, an OUT electrode (120), a ground electrode (121), and a Vcc1 electrode (122) are disposed on the n - type region (101). The Vcc1 electrode (122) is connected to the positive electrode of an auxiliary direct current power supply (a bootstrap capacitor) (E1). The OUT electrode (120) is connected to the negative electrode of the auxiliary direct current power supply (E1). One end portion (a second contact portion) (403) of the high resistance polysilicon thin film (401) is connected to the ground electrode (121). Also, the other end portion (a first contact portion) (402) of the high resistance polysilicon thin film (401) is connected to the OUT electrode (120).
摘要翻译： n型区域（101）包围有n型阱区域（201），其中设置有高侧驱动电路（300）。构成高击穿电压结终止区域的电阻场板结构的高电阻多晶硅薄膜（401）以螺旋形式设置在n型区域（101）上。此外，在n型区域（101）上设置有OUT电极（120），接地电极（121）和Vcc1电极（122）。 Vcc1电极（122）与辅助直流电源（自举电容器）（E1）的正极连接。 OUT电极（120）与辅助直流电源（E1）的负极连接。高电阻多晶硅薄膜（401）的一个端部（第二接触部分）（403）连接到接地电极121。此外，高电阻多晶硅薄膜（401）的另一端部（第一接触部分）（402）连接到OUT电极（120）。

5. 发明公开

EP2581938A4 HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE 有权
标题翻译：带集成电路的高压设备
公开(公告)号：EP2581938A4
公开(公告)日：2014-12-31
申请号：EP12757637
申请日：2012-03-13
申请人： FUJI ELECTRIC CO LTD
发明人： YAMAJI MASAHARU
IPC分类号： H01L21/761 , G05F3/02 , H01L27/092
CPC分类号： G05F3/02 , H01L21/761 , H01L27/0921 , H01L27/0922
摘要： A high-voltage integrated circuit device (100) comprises, in a surface layer of a p semiconductor substrate (1), an n region (3) which is a high-side floating-potential region, an n - region (4) which becomes a high-voltage junction terminating region (93), and an n - region (2) which is an L-VDD potential region. A low-side circuit portion (91) is disposed in an n - region (2). Below a pickup electrode (59) disposed in the high-voltage junction terminating region (93), a universal contact region (58) in Ohmic contact with the pickup electrode is disposed. The universal contact region (58) has a p + region (56) and an n + region (57) that are disposed in alternating contact along a surface of the p semiconductor substrate (1). By disposing the universal contact region (58) in this way, the quantity of carriers flowing into the low-side circuit portion (91) can be reduced when a negative surge voltage is input. Consequently, erroneous operation and destruction due to latchup of a logic portion of the low-side circuit portion (91) can be prevented.
摘要翻译：高电压集成电路器件（100）在p型半导体衬底（1）的表面层中包括作为高侧浮动电位区域的n区域（3），成为高压结端接区域（93）和作为L-VDD电势区域的n区域（2）。低侧电路部分（91）设置在n区（2）中。在设置在高压结终止区域（93）中的拾取电极（59）的下方设置有与拾取电极欧姆接触的通用接触区域（58）。通用接触区域（58）具有沿着p半导体衬底（1）的表面交替接触地设置的p +区域（56）和n +区域（57）。通过以这种方式设置通用接触区域（58），当输入负浪涌电压时，流入低侧电路部分（91）的载流子的数量可以减少。因此，可以防止由于低侧电路部分（91）的逻辑部分的闭锁而导致的错误操作和破坏。

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