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1. 发明公开

EP3043387A1 INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR 有权转让
标题翻译：绝缘栅双极型晶体管及其制造方法
公开(公告)号：EP3043387A1
公开(公告)日：2016-07-13
申请号：EP14840868.5
申请日：2014-08-25
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： ZHONG, Shengrong , ZHOU, Dongfei , DENG, Xiaoshe , WANG, Genyi
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) are disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51). A P-type heavily doped region (71) is disposed in the N-type heavily doped region (61). An inward recessed shallow pit (62) with a depth of 0.15 to 0.3 micrometers is formed on a surface of the P-type heavily doped region (71). By disposing the carrier enhancement region (41), the carrier concentration of a channel can be increased and a forward voltage drop can be reduced; in addition, the shallow pit (62) can make a device obtain good impurity distribution and a large metal contact area, thereby improving the performance of the device.
摘要翻译：提供绝缘栅双极晶体管（100）。绝缘栅双极型晶体管（100）的衬底（10）是N型的。 P型区域（16）设置在N型衬底的背面。背面金属结构（18）设置在P型区域（16）的背面。终端保护环设置在终端结构中。多晶硅栅极（31）设置在衬底（10）的有源区中的前表面上。侧壁（72）设置在衬底（10）上的多晶硅栅极（31）的两侧。在衬底（10）上设置覆盖有多晶硅栅极（31）和侧壁（72）的层间介质（81）。层间介质（81）被金属引线层（91）覆盖。 N型载流子增强区（41）设置在有源区中的衬底（10）中。载波增强区（41）中设置有P型体区（51）。 N型重掺杂区（61）设置在P型体区（51）中。 P型重掺杂区（71）设置在N型重掺杂区（61）中。在P型重掺杂区（71）的表面上形成深度为0.15至0.3微米的向内凹陷的浅坑（62）。通过设置载流子增强区域（41），可以增加沟道的载流子浓度，并且可以降低正向压降; 此外，浅槽（62）可以使器件获得良好的杂质分布和大的金属接触面积，从而提高器件的性能。

2. 发明公开

EP3016144A1 FIELD-STOP REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR 有权转让
标题翻译：落后及主要场站绝缘栅及其制造方法双极型晶体管
公开(公告)号：EP3016144A1
公开(公告)日：2016-05-04
申请号：EP14816878.4
申请日：2014-06-05
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： ZHANG, Shuo , RUI, Qiang , WANG, Genyi , DENG, Xiaoshe
IPC分类号： H01L29/73 , H01L21/02
摘要： A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).

3. 发明授权

EP2709142B1 Method for forming a PN superjunction 有权转让
标题翻译：形成PN超级结的方法
公开(公告)号：EP2709142B1
公开(公告)日：2016-03-23
申请号：EP12796409.6
申请日：2012-05-31
申请人： CSMC Technologies Fab1 Co., Ltd. , CSMC Technologies Fab2 Co., Ltd.
发明人： WU, Tzong Shiann , WANG, Genyi , YUAN, Leibing , WU, Pengpeng
IPC分类号： H01L29/06 , H01L21/3065
CPC分类号： H01L29/66136 , H01L21/3065 , H01L29/0619 , H01L29/0634

4. 发明公开

EP3041036A1 METHOD FOR MANUFACTURING INSULATED GATE BIPOLAR TRANSISTOR 有权转让
标题翻译：用于生产BIPOLAR绝缘栅晶体管
公开(公告)号：EP3041036A1
公开(公告)日：2016-07-06
申请号：EP14839057.8
申请日：2014-08-25
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： ZHONG, Shengrong , ZHOU, Dongfei , DENG, Xiaoshe , WANG, Genyi
IPC分类号： H01L21/331
摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a poly silicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.

5. 发明公开

EP3002781A1 MANUFACTURING METHOD FOR REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR 有权转让
标题翻译： BERSOLAREN晶体管MIT ISOLIERTEM GATE HERTELLUNGSVERFAHRENFÜRRÜCKWÄRTSLEITEENEN
公开(公告)号：EP3002781A1
公开(公告)日：2016-04-06
申请号：EP14838639.4
申请日：2014-08-19
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： ZHANG, Shuo , RUI, Qiang , WANG, Genyi , DENG, Xiaoshe
IPC分类号： H01L21/331
CPC分类号： H01L27/0664 , H01L21/263 , H01L21/26513 , H01L21/304 , H01L21/3065 , H01L29/0638 , H01L29/0834 , H01L29/1095 , H01L29/66333 , H01L29/7395
摘要： A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.
摘要翻译：一种用于反向导通绝缘栅双极晶体管的制造方法，其制造方法的特征在于使用多晶硅来填充反向导通绝缘栅双极晶体管背面的沟槽。反向导通绝缘栅双极晶体管背面的反向导通二极管的参数可以通过精确控制多晶硅的掺杂浓度来简单地控制，从而对过程控制要求相对较低。反向导通绝缘栅双极晶体管制造方法对于工艺控制的要求相对较低，制造难度相对较小。

6. 发明公开

EP3026695A1 METHOD FOR MANUFACTURING INJECTION-ENHANCED INSULATED-GATE BIPOLAR TRANSISTOR 有权转让
标题翻译：用于生产注射法ENHANCED绝缘栅双极晶体管
公开(公告)号：EP3026695A1
公开(公告)日：2016-06-01
申请号：EP14829488.7
申请日：2014-07-23
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： WANG, Wanli , DENG, Xiaoshe , WANG, Genyi , HUANG, Xuan
IPC分类号： H01L21/331 , H01L29/73 , H01L29/78
CPC分类号： H01L29/66348 , H01L21/2253 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L29/063 , H01L29/1095 , H01L29/7397
摘要： A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.

7. 发明公开

EP3016142A1 IGBT WITH BUILT-IN DIODE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：具有内置二极管的IGBT及其制造方法
公开(公告)号：EP3016142A1
公开(公告)日：2016-05-04
申请号：EP14817399.0
申请日：2014-06-09
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： DENG, Xiaoshe , ZHANG, Shuo , RUI, Qiang , WANG, Genyi
IPC分类号： H01L29/06 , H01L29/739
CPC分类号： H01L27/0727 , H01L21/8249 , H01L29/0619 , H01L29/0684 , H01L29/0834 , H01L29/402 , H01L29/66333 , H01L29/7395 , H01L29/868
摘要： An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1S1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1S2) of the semiconductor substrate (1) alternately, wherein the IGBT only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1 S2) of the semiconductor substrate (1).
摘要翻译：提供了具有内置二极管的绝缘栅双极型转换器（IGBT）及其制造方法。 IGBT包括：具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括有源区（100）和端子保护区域（200），其位于有源区域的外侧; 绝缘栅晶体管单元，其形成在所述有源区域的所述第一主表面的侧面，其中在所述有源区域的导电期间形成所述第一导电类型的沟道; 和形成在半导体衬底（1）的第二主表面（1S2）侧的第一导电类型和第二导电类型的有源区域的第二半导体层（11）的第一半导体层（10）或者其中IGBT仅在位于半导体衬底（1）的第二主表面（S1S）侧的端子保护区域（200）中包括第二半导体层（11）。

8. 发明公开

EP2879168A1 METHOD FOR REMOVING POLYCRYSTALLINE SILICON PROTECTING LAYER ON IGBT BACK FACE HAVING FIELD TERMINATION STRUCTURE 有权转让
标题翻译： METHOD FOR REMOVING多晶硅IGBT构成的保护层上框架组件的背
公开(公告)号：EP2879168A1
公开(公告)日：2015-06-03
申请号：EP13822946.3
申请日：2013-07-25
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： RUI, Qiang , ZHANG, Shuo , WANG, Genyi , DENG, Xiaoshe
IPC分类号： H01L21/331 , H01L21/3105 , H01L21/04
CPC分类号： H01L21/31116 , H01L21/32105 , H01L21/32137 , H01L29/66325 , H01L29/66333
摘要： Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.
摘要翻译：公开了一种用于在具有一个视场光阑结构（10）的IGBT的背面去除多晶硅层保护（12）的方法。该方法包括热氧化在IGBT的背面上的多晶硅保护层（12），直到氧化终止位于多晶硅保护层（12）之上的栅极氧化物层（11）上，以形成二氧化硅层（13）并除去所形成的二氧化硅层（13），并通过干法蚀刻工艺的栅极氧化物层（11）。用于移除保护层的方法，是更容易控制。

9. 发明公开

EP2709142A1 METHOD FOR FORMING DEEP-CHANNEL SUPER-PN JUNCTION 有权转让
标题翻译： Verfahren zur Bildung eines PN-Superübergangs
公开(公告)号：EP2709142A1
公开(公告)日：2014-03-19
申请号：EP12796409.6
申请日：2012-05-31
申请人： CSMC Technologies Fab1 Co., Ltd. , CSMC Technologies Fab2 Co., Ltd.
发明人： WU, Tzong Shiann , WANG, Genyi , YUAN, Leibing , WU, Pengpeng
IPC分类号： H01L21/04 , H01L21/31 , H01L21/336
CPC分类号： H01L29/66136 , H01L21/3065 , H01L29/0619 , H01L29/0634
摘要： The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a depostion step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.
摘要翻译：本发明提供一种用于制造深沟槽超PN结的方法。该方法包括：用于在衬底上形成外延层的沉积步骤; 在外延层上依次形成第一电介质层和第二电介质层; 在外延层中形成深沟槽; 用外延材料完全填充深沟槽，并且外延材料超出第二介电层; 使用第三电介质填充第二电介质层的整个表面和诸如Si的外延层从具有预定高度的表面填充层填充; 在表面填充层上回蚀刻到第一介电层和外延层的界面; 以及去除第一电介质层，第二介电层和表面填充层以使Si外延材料平坦化的去除步骤。

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