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1. 发明公开

EP1487024A1 LATERAL JUNCTIION FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD 审中-公开
标题翻译： VERFAHREN ZU SEINER HERSTELLUNG的侧边球员
公开(公告)号：EP1487024A1
公开(公告)日：2004-12-15
申请号：EP02786001.4
申请日：2002-12-02
申请人： SUMITOMO ELECTRIC INDUSTRIES, Ltd
发明人： FUJIKAWA, Kazuhiro, c/o SUMITOMO ELEC. IND., LTD , HARADA, Shin, c/o SUMITOMO ELEC. IND., LTD , HIROTSU, Kenichi, c/o SUMITOMO ELEC. IND., LTD , HATSUKAWA, Satoshi, c/o SUMITOMO ELEC. IND., LTD , HOSHINO, Takashi, c/o SUMITOMO ELEC. IND., LTD , MATSUNAMI, Hiroyuki , KIMOTO, Tsunenobu
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/0634 , H01L29/1058 , H01L29/1066 , H01L29/42316 , H01L29/66893 , H01L29/808
摘要： A lateral junction field effect transistor includes a first gate electrode layer (18A) arranged in a third semiconductor layer (13) between source/drain region layers (6, 8), having a lower surface extending on the second semiconductor layer (12), and doped with p-type impurities more heavily than the second semiconductor layer (12), and a second gate electrode layer (18B) arranged in a fifth semiconductor layer (15) between the source/drain region layers (6, 8), having a lower surface extending on a fourth semiconductor layer (14), having substantially the same concentration of p-type impurities as the first gate electrode layer (18A), and having the same potential as the first gate electrode layer (18A). Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
摘要翻译：横向结型场效应晶体管包括布置在源极/漏极区域（6,8）之间的第三半导体层（13）中的第一栅电极层（18A），其具有在第二半导体层（12）上延伸的下表面，并且掺杂有比第二半导体层（12）更重的p型杂质;以及布置在源极/漏极区域（6,8）之间的第五半导体层（15）中的第二栅极电极层（18B），具有在第四半导体层（14）上延伸的下表面，具有与第一栅电极层（18A）基本相同的p型杂质浓度，并具有与第一栅电极层（18A）相同的电位。因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

2. 发明授权

EP0354372B1 Plurality of thin film field-effect transistors and method of manufacturing the same 失效
标题翻译：薄膜场效应晶体管和它们的制备方法的多个。
公开(公告)号：EP0354372B1
公开(公告)日：1994-04-06
申请号：EP89112789.6
申请日：1989-07-12
申请人： AGENCY OF INDUSTRIAL SCIENCE AND TECHNOLOGY
发明人： Hayashi, Yutaka Electrotech. Lab. Agency of , Yamanaka, Mitsuyuki Electrotech. Lab. Agency of , Yoshimi, Takashi
IPC分类号： H01L27/12 , H01L29/784 , H01L29/808
CPC分类号： H01L29/78696 , H01L21/84 , H01L29/432 , H01L29/66757 , H01L29/66848 , H01L29/66893 , H01L29/78663 , H01L29/8086 , H01L29/8126

3. 发明公开

EP1487024A4 LATERAL JUNCTIION FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD 审中-公开
标题翻译： LATERAL-BARRIER场效应晶体管及其制造方法
公开(公告)号：EP1487024A4
公开(公告)日：2009-10-21
申请号：EP02786001
申请日：2002-12-02
申请人： SUMITOMO ELECTRIC INDUSTRIES
发明人： FUJIKAWA KAZUHIRO , HARADA SHIN , HIROTSU KENICHI , HATSUKAWA SATOSHI , HOSHINO TAKASHI , MATSUNAMI HIROYUKI , KIMOTO TSUNENOBU
IPC分类号： H01L29/808 , H01L21/337 , H01L29/10 , H01L29/423
CPC分类号： H01L29/0634 , H01L29/1058 , H01L29/1066 , H01L29/42316 , H01L29/66893 , H01L29/808

4. 发明公开

EP3047523A1 HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES 有权
标题翻译： HOCHSPANNUNGS-MOSFET-VORRICHTUNGEN UND VERFAHREN ZUR HERSTELLUNG DER ANORDNUNGEN
公开(公告)号：EP3047523A1
公开(公告)日：2016-07-27
申请号：EP14846166.8
申请日：2014-09-18
申请人： Monolith Semiconductor Inc.
发明人： BANERJEE, Sujit , MATOCHA, Kevin , CHATTY, Kiran
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/046 , H01L21/22 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/4238 , H01L29/456 , H01L29/6606 , H01L29/66068 , H01L29/66712 , H01L29/66893 , H01L29/7802 , H01L29/7806 , H01L29/8083
摘要： A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.
摘要翻译：描述具有低比电阻的SiC MOSFET器件。该器件具有在一个方向（Y方向）上延伸的N +，P阱和JFET区域，并且P +和源极触点沿正交方向（X方向）延伸。该器件的多晶硅栅极覆盖JFET区并且终止于P阱区上，以最小化多晶硅栅极边缘处的电场。在使用中，电流从结构底部的漏极接触垂直流入JFET区域，然后在X方向横向通过累积区域并通过MOSFET沟道进入相邻的N +区域。流出通道的电流随后沿着Y方向的N +区流动，并由源触点和最终金属收集。还描述了制造该装置的方法。

5. 发明公开

EP0354372A1 Plurality of thin film field-effect transistors and method of manufacturing the same 失效
标题翻译： Mehrzahl vonDünnfilmfeldeffekttransistorenund Verfahren zu ihrer Herstellung。
公开(公告)号：EP0354372A1
公开(公告)日：1990-02-14
申请号：EP89112789.6
申请日：1989-07-12
申请人： AGENCY OF INDUSTRIAL SCIENCE AND TECHNOLOGY
发明人： Hayashi, Yutaka Electrotech. Lab. Agency of , Yamanaka, Mitsuyuki Electrotech. Lab. Agency of , Yoshimi, Takashi
IPC分类号： H01L27/12 , H01L29/784 , H01L29/808
CPC分类号： H01L29/78696 , H01L21/84 , H01L29/432 , H01L29/66757 , H01L29/66848 , H01L29/66893 , H01L29/78663 , H01L29/8086 , H01L29/8126
摘要： A thin film field effect transistor comprising a source electrode (6) and a drain electrode (7) joined to a first semiconductor layer (4) respectively through the spaced apart second semiconductor layers (5a, 5b) of a second semiconductor layer (5) of a doped semiconductor, a gate insulating layer (3), and a gate electrode (2) capacity-coupled through the gate insulating layer (3) with a portion of the first semiconductor layer (4), in which a channel (8) is formed, corresponding to a gap between the source electrode (6) and the drain electrode (7). A doped intermediate semiconductor layer (9 or 10) is formed in contact with the channel (8) in the first semiconductor layer (4). The gate threshold voltage of the thin film field effect transistor can be decided optionally by selectively deciding the thickness of the doped intermediate semiconductor layer (9 or 10). Thus, a plurality of thin film field effect transistors respectively having different gate threshold voltages can be formed on a single substrate simply by forming the doped intermediate semiconductor layers (9 or 10) for the thin film field effect transistors in different thicknesses.
摘要翻译：一种薄膜场效应晶体管，包括分别通过第二半导体层（5）的间隔开的第二半导体层（5a，5b）连接到第一半导体层（4）的源电极（6）和漏电极（7）掺杂半导体的栅极绝缘层（3）和通过栅极绝缘层（3）与第一半导体层（4）的一部分电容耦合的栅电极（2），其中沟道（8）形成，对应于源电极（6）和漏电极（7）之间的间隙。掺杂的中间半导体层（9或10）形成为与第一半导体层（4）中的沟道（8）接触。可以通过选择性地决定掺杂中间半导体层（9或10）的厚度来决定薄膜场效应晶体管的栅极阈值电压。因此，仅通过形成不同厚度的薄膜场效应晶体管的掺杂中间半导体层（9或10），可以在单个衬底上形成分别具有不同栅极阈值电压的多个薄膜场效应晶体管。

6. 发明公开

EP3047523A4 HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES 有权
公开(公告)号：EP3047523A4
公开(公告)日：2017-10-18
申请号：EP14846166
申请日：2014-09-18
申请人： MONOLITH SEMICONDUCTOR INC
发明人： BANERJEE SUJIT , MATOCHA KEVIN , CHATTY KIRAN
IPC分类号： H01L29/78 , H01L21/336 , H01L29/08 , H01L29/423
CPC分类号： H01L29/7827 , H01L21/046 , H01L21/22 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/42356 , H01L29/4238 , H01L29/456 , H01L29/6606 , H01L29/66068 , H01L29/66712 , H01L29/66893 , H01L29/7802 , H01L29/7806 , H01L29/8083
摘要： A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

7. 发明公开

EP3136426A1 METHOD FOR PRODUCING A JUNCTION FIELD EFFECT TRANSISTOR ON A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：用于生产TRANSITION场效应晶体管在半导体基板
公开(公告)号：EP3136426A1
公开(公告)日：2017-03-01
申请号：EP15182155.0
申请日：2015-08-24
申请人： IMEC VZW
发明人： Hellings, Geert , Van der Plas, Geert , Scholz, Mirko
IPC分类号： H01L21/337 , H01L29/808 , H01L29/10 , H01L21/265 , H01L29/861 , H01L21/329 , H01L21/761
CPC分类号： H01L27/0928 , H01L21/0332 , H01L21/265 , H01L21/266 , H01L21/761 , H01L27/0629 , H01L27/098 , H01L29/1058 , H01L29/456 , H01L29/66128 , H01L29/66893 , H01L29/66901 , H01L29/808 , H01L29/8611
摘要： The invention is related to a method for producing a junction field effect transistor on a semiconductor substrate, wherein the steps of depositing a pre-metal dielectric layer and producing contact openings in said PMD layer precede the step of implanting a well with dopants of a first and second type and wherein the thickness of the PMD layer is configured so that a channel is created by implanting dopants through the PMD layer. The method of the invention allows to produce the JFET on an interposer substrate using a limited number of lithographic masks.
摘要翻译：本发明涉及一种方法，用于在半导体基板制造结型场效应晶体管，worin在说PMD层上沉积预金属电介质层和制造接触开口的步骤先于植入的阱与第一类型的掺杂剂的步骤和第二类型和worin PMD层的厚度，做了一个信道是通过PMD层注入掺杂剂在已配置。本发明的方法允许生产到使用光刻掩膜有限数量内插基板的JFET。

8. 发明公开

EP2782122A3 Manufacturing method of JFET semiconductor device and JFET semiconductor device 有权转让
标题翻译：一种制造半导体JFET装置及半导体装置JFET的方法
公开(公告)号：EP2782122A3
公开(公告)日：2014-12-24
申请号：EP14160755.6
申请日：2014-03-19
申请人： Renesas Electronics Corporation
发明人： Kagotoshi, Yasuaki , Arai, Koichi , Yokoyama, Natsuki , Shimizu, Haruka
IPC分类号： H01L21/337 , H01L29/808
CPC分类号： H01L29/0619 , H01L29/1066 , H01L29/1608 , H01L29/42316 , H01L29/66068 , H01L29/66893 , H01L29/8083
摘要： A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n + -type source layer on a surface of an n - -type drift layer formed on an n + -type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n - -type drift layer with a silicon oxide film formed on the n - -type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n - -type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n - -type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

9. 发明公开

EP2782122A2 Manufacturing method of JFET semiconductor device and JFET semiconductor device 有权转让
标题翻译： JFET半导体器件和JFET半导体器件的制造方法
公开(公告)号：EP2782122A2
公开(公告)日：2014-09-24
申请号：EP14160755.6
申请日：2014-03-19
申请人： Renesas Electronics Corporation
发明人： Kagotoshi, Yasuaki , Arai, Koichi , Yokoyama, Natsuki , Shimizu, Haruka
IPC分类号： H01L21/337 , H01L29/808
CPC分类号： H01L29/0619 , H01L29/1066 , H01L29/1608 , H01L29/42316 , H01L29/66068 , H01L29/66893 , H01L29/8083
摘要： A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n + -type source layer on a surface of an n - -type drift layer formed on an n + -type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n - -type drift layer with a silicon oxide film formed on the n - -type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n - -type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n - -type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.
摘要翻译：一种结型场效应晶体管的制造方法包括以下步骤：（a）在形成于n +型SiC衬底上的n型漂移层的表面上形成n +型源极层; （b）通过蚀刻n-型漂移层的表面，以形成在n-型漂移层上的氧化硅膜作为掩模，以预定间隔形成多个浅沟槽; （c）通过使用垂直离子注入方法用氮在每个浅沟槽下方掺杂n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入方法在每个浅沟槽下面用铝掺杂所述n-型漂移层来形成p-型栅极层。

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