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1. 发明公开

EP3373329A1 LATERALLY DIFFUSED MOS FIELD EFFECT TRANSISTOR 有权
公开(公告)号：EP3373329A1
公开(公告)日：2018-09-12
申请号：EP18159759.2
申请日：2014-02-28
申请人： LFoundry S.r.l.
发明人： Spitzlsperger, Gerhard , Schmidt, Carsten
IPC分类号： H01L21/768 , H01L29/78 , H01L21/74 , H01L21/762 , H01L29/66 , H01L29/417 , H01L21/8234
CPC分类号： H01L23/562 , H01L21/743 , H01L21/76224 , H01L21/76898 , H01L21/823418 , H01L23/5226 , H01L23/528 , H01L24/43 , H01L27/092 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41708 , H01L29/4175 , H01L29/41766 , H01L29/66272 , H01L29/66333 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/732 , H01L29/7395 , H01L29/7398 , H01L29/74 , H01L29/7802 , H01L29/7811 , H01L29/7816 , H01L29/7823 , H01L29/7824 , H01L29/7835 , H01L29/808 , H01L2224/4502
摘要： A method of fabricating a semiconductor product includes the processing of a semiconductor wafer (10) from a front surface including structures disposed in the substrate (100) of the wafer adjacent to the front surface and the forming of at least one wiring (110) embedded in a dielectric layer (111) disposed on the front surface of the wafer. The semiconductor wafer is mounted to a carrier wafer (120) at its front surface so that material can be removed from the backside of the wafer to thin the semiconductor wafer. Backside processing of the semiconductor wafer includes the forming of implantations from the backside of the wafer, the forming of deep trenches (132a, 132b) to isolate the structures from other structures within the wafer, the forming of a through silicon via (134) to contact features on the frontside of the wafer and the forming of a body contact (131). Several devices, for example a LDMOS transistor with a field plate formed on the thinned backside, can be generated within the same wafer.

2. 发明授权

EP1753693B1 TAP UNIT FOR A BEVERAGE DISPENSER 有权转让
标题翻译：用于饮料分配器的TAP单元
公开(公告)号：EP1753693B1
公开(公告)日：2018-03-14
申请号：EP05736233.7
申请日：2005-05-11
申请人： Koninklijke Philips N.V.
发明人： RAMUSCH, Adolf , HAEFELE, Peter , IGERC, Marc
IPC分类号： B67D1/14
CPC分类号： B67D1/1422 , H01L29/1095 , H01L29/66333 , H01L29/7395
摘要： The present invention relates to a cartridge unit for a beverage dispensing system with an inner channel for the dispensation of a beverage, characterized in that the cartridge unit comprises a first part, which is made of an inflexible material and a second part, which is made of a flexible material.

3. 发明公开

EP3195363A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A THIN SEMICONDUCTOR WAFER 有权转让
标题翻译：制造包含薄半导体晶片的半导体器件的方法
公开(公告)号：EP3195363A1
公开(公告)日：2017-07-26
申请号：EP15766093.7
申请日：2015-09-11
申请人： ABB Schweiz AG
发明人： JANISCH, Wolfgang , DE VRIES, Atze , MATTHIAS, Sven
IPC分类号： H01L29/66 , H01L21/762 , H01L21/225 , H01L29/739 , H01L29/744 , H01L29/08 , H01L21/20
CPC分类号： H01L21/225 , H01L21/2007 , H01L21/2253 , H01L21/2256 , H01L21/283 , H01L21/673 , H01L21/76256 , H01L29/0834 , H01L29/0873 , H01L29/66333 , H01L29/66363 , H01L29/7395 , H01L29/744
摘要： A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side of a semiconductor wafer. A first oxide layer is formed on the first main side of the wafer, wherein the first oxide layer is partially doped with a second impurity in such way that any first portion of the first oxide layer which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer and the first main side of the semiconductor wafer. Thereafter a carrier wafer is bonded to the first oxide layer. During front-end-of-line processing on the second main side of the semiconductor wafer, the second impurity is diffused from the first oxide layer into the semiconductor wafer from its first main side by heat generated during the front-end-of-line processing.
摘要翻译：提供了一种用于制造垂直功率半导体器件的方法，其中在半导体晶片（101）的第一主侧（103）处提供第一杂质。第一氧化物层（112）形成在晶片（101）的第一主侧面（103）上，其中第一氧化物层（112）部分地掺杂有第二杂质，使得第一氧化物掺杂有第二杂质的第一层（112）通过未掺杂第二杂质的第一氧化物层（112）的第二部分与半导体晶片隔开并且设置在第一氧化物的第一部分层（112）和半导体晶片（101）的第一主侧（103）。此后，载体晶片（115）结合到第一氧化物层（112）。在半导体晶片（101）的第二主侧（102）上的前端处理期间，第二杂质从第一氧化物层（112）从其第一主侧（111）扩散到半导体晶片（103）通过在生产线前端处理期间产生的热量。

4. 发明公开

EP3041036A4 METHOD FOR MANUFACTURING INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES BIPOLAREN TRANSISTORS MIT ISOLIERTEM GATE
公开(公告)号：EP3041036A4
公开(公告)日：2017-01-25
申请号：EP14839057
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO LTD
发明人： ZHONG SHENGRONG , ZHOU DONGFEI , DENG XIAOSHE , WANG GENYI
IPC分类号： H01L21/331 , H01L29/06 , H01L29/10 , H01L29/739
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/401 , H01L29/407 , H01L29/408 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a poly silicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.
摘要翻译：一种绝缘栅双极型晶体管（100）的制造方法，其特征在于，在基板（10）的前表面形成基板（10），形成场氧化物层（20），形成端子保护环（23）。通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并进行结合推压然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P-体区域，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。该方法减少了设置载流子增强区域的正向压降。

5. 发明公开

EP3002781A4 MANUFACTURING METHOD FOR REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译：方法逆转与绝缘栅双极晶体管CONDUCTING
公开(公告)号：EP3002781A4
公开(公告)日：2017-01-25
申请号：EP14838639
申请日：2014-08-19
申请人： CSMC TECHNOLOGIES FAB1 CO LTD
发明人： ZHANG SHUO , RUI QIANG , WANG GENYI , DENG XIAOSHE
IPC分类号： H01L21/331 , H01L29/08 , H01L29/32 , H01L29/739
CPC分类号： H01L27/0664 , H01L21/263 , H01L21/26513 , H01L21/304 , H01L21/3065 , H01L29/0638 , H01L29/0834 , H01L29/1095 , H01L29/66333 , H01L29/7395
摘要： A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

6. 发明公开

EP3016142A4 IGBT WITH BUILT-IN DIODE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译： IGBT MIT EINGEBAUTER DIODE UND HERSTELLUNGSVERFAHRENDAFÜR
公开(公告)号：EP3016142A4
公开(公告)日：2016-12-14
申请号：EP14817399
申请日：2014-06-09
申请人： CSMC TECHNOLOGIES FAB1 CO LTD
发明人： DENG XIAOSHE , ZHANG SHUO , RUI QIANG , WANG GENYI
IPC分类号： H01L29/06 , H01L29/08 , H01L29/66 , H01L29/739
CPC分类号： H01L27/0727 , H01L21/8249 , H01L29/0619 , H01L29/0684 , H01L29/0834 , H01L29/402 , H01L29/66333 , H01L29/7395 , H01L29/868

7. 发明公开

EP2923375A4 DEVICE ARCHITECTURE AND METHOD FOR PRECISION ENHANCEMENT OF VERTICAL SEMICONDUCTOR DEVICES 审中-公开
标题翻译：装备体系和方法改进精密立式半导体器件
公开(公告)号：EP2923375A4
公开(公告)日：2016-07-20
申请号：EP13856431
申请日：2013-11-26
申请人： D3 SEMICONDUCTOR LLC
发明人： HARRINGTON THOMAS E III
IPC分类号： H01L21/66 , H01L23/525 , H01L27/088
CPC分类号： H01L23/5256 , H01L22/14 , H01L22/20 , H01L23/5258 , H01L27/0629 , H01L27/088 , H01L27/11206 , H01L28/20 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7827 , H01L2924/0002 , H01L2924/00

8. 发明公开

EP2541604A4 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR 审中-公开
公开(公告)号：EP2541604A4
公开(公告)日：2016-04-20
申请号：EP10846515
申请日：2010-02-25
申请人： RENESAS ELECTRONICS CORP
发明人： ARAI DAISUKE , NAKAZAWA YOSHITO , HOSOYA NORIO
IPC分类号： H01L29/739 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/40 , H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7395 , H01L24/05 , H01L29/0653 , H01L29/0696 , H01L29/402 , H01L29/66333 , H01L2224/04042 , H01L2224/45144 , H01L2224/48463 , H01L2224/73265 , H01L2924/13055 , H01L2924/14 , H01L2924/00

9. 发明公开

EP2939271A1 SEMICONDUCTOR DEVICES HAVING REDUCED ELECTRIC FIELD AT A GATE OXIDE LAYER 有权
标题翻译： HALBLEITERBAUELEMENTE MIT EINEM REDUZIERTEN ELEKTRISCHEN FELD AN EINER GATE-OXID-SCHICHT
公开(公告)号：EP2939271A1
公开(公告)日：2015-11-04
申请号：EP13811320.4
申请日：2013-12-04
申请人： Cree, Inc.
发明人： ZHANG, Qingchun , HULL, Brett
IPC分类号： H01L29/78 , H01L29/739 , H01L29/749 , H01L29/06 , H01L21/336 , H01L21/331 , H01L21/332 , H01L29/16
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0623 , H01L29/0688 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66333 , H01L29/66378 , H01L29/66666 , H01L29/66712 , H01L29/7395 , H01L29/749 , H01L29/7827 , H01L29/7828
摘要： A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.
摘要翻译：公开了一种在栅极氧化物界面处具有减小的电场的晶体管器件。在一个实施例中，晶体管器件包括栅极，源极和漏极，其中栅极至少部分地与栅极氧化物接触。晶体管器件在晶体管器件的JFET区域内具有P +区域，以便减小栅极氧化物上的电场。

10. 发明公开

EP2793268A4 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP2793268A4
公开(公告)日：2015-08-19
申请号：EP13769834
申请日：2013-03-29
申请人： FUJI ELECTRIC CO LTD
发明人： MIYAZAKI MASAYUKI , YOSHIMURA TAKASHI , TAKISHITA HIROSHI , KURIBAYASHI HIDENAO
IPC分类号： H01L29/739 , H01L21/265 , H01L21/329 , H01L21/336 , H01L29/08 , H01L29/66 , H01L29/78 , H01L29/868
CPC分类号： H01L29/66348 , H01L21/26 , H01L21/26513 , H01L21/3003 , H01L29/32 , H01L29/36 , H01L29/66128 , H01L29/66333 , H01L29/7393 , H01L29/7397 , H01L29/8611
摘要： A p + collector layer is provided in a surface layer of a rear surface of a semiconductor substrate which will be an n- drift layer and an n + field stop layer is provided in a region which is deeper than the p + collector layer formed on the rear surface. A collector electrode comes into contact with the p + collector layer. When the p + collector layer and the n + field stop layer are formed, impurity ions are implanted into the rear surface of the semiconductor substrate (Step S5). Then, a first annealing process is performed to activate the impurity ions, thereby forming the p + collector layer (Step S6). Then, a proton is radiated to the rear surface of the semiconductor substrate (Step S7). Then, a second annealing process is performed to change the proton into a donor, thereby forming the field stop layer (Step S8). The first annealing process is performed at a higher annealing temperature than the second annealing process. Then, a collector electrode is formed on the rear surface of the semiconductor substrate (Step S9). Therefore, it is possible to prevent deterioration of electrical characteristics.

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