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1. 发明公开

EP3170207A4 SOLID-SOURCE DIFFUSED JUNCTION FOR FIN-BASED ELECTRONICS 无效转让
公开(公告)号：EP3170207A4
公开(公告)日：2018-03-28
申请号：EP14897867
申请日：2014-07-14
申请人： INTEL CORP
发明人： HAFEZ WALID M , JAN CHIA HONG
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/0649 , H01L27/098 , H01L29/0657 , H01L29/404 , H01L29/66166 , H01L29/66803 , H01L29/66901 , H01L29/808 , H01L29/8605
摘要： A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

2. 发明公开

EP2375451A3 Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors 审中-公开
标题翻译：侧沟槽Feldeffektortransistoren在半导体材料中具有宽带隙，它们的制造方法以及与晶体管集成电路
公开(公告)号：EP2375451A3
公开(公告)日：2012-04-18
申请号：EP11173329.1
申请日：2005-11-30
申请人： SS SC IP, LLC
发明人： Sankin, Igor , Casady, Jeffrey. B , Merrett, Joseph N.
IPC分类号： H01L29/423 , H01L29/808 , H01L27/098 , H01L29/812 , H01L29/20 , H01L29/24 , H01L29/47
CPC分类号： H01L29/2003 , H01L27/098 , H01L29/1608 , H01L29/47 , H01L29/808 , H01L29/8122
摘要： A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The junction field effect transistor comprises source, channel, drift, and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift, and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions, can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits com rising the devices are also described.

3. 发明公开

EP1829113A4 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 有权
标题翻译：常闭JFET集成电路与BIG BAND距离和方法SEMICONDUCTORS
公开(公告)号：EP1829113A4
公开(公告)日：2011-06-15
申请号：EP05849440
申请日：2005-11-30
申请人： SEMISOUTH LAB INC
发明人： SANKIN IGOR , MERRETT JOSEPH N
IPC分类号： H01L29/76
CPC分类号： H03K17/567 , H01L27/098 , H01L29/1608 , H01L29/2003 , H01L29/808 , H01L29/8083 , H01L29/8086 , H01L29/861 , H01L29/868 , H01L29/872

4. 发明公开

EP2067170A1 HALBLEITERANORDNUNG MIT GEKOPPELTEN SPERRSCHICHT- FELDEFFEKTTRANSISTOREN 审中-公开
标题翻译：耦合结型场效应晶体管功率半导体装置
公开(公告)号：EP2067170A1
公开(公告)日：2009-06-10
申请号：EP07820405.4
申请日：2007-09-20
申请人： SiCED Electronics Development GmbH & Co KG
发明人： FRIEDRICHS, Peter , STEPHANI, Dietrich
IPC分类号： H01L27/098 , H03K17/082 , H01L27/02 , H01L29/808
CPC分类号： H01L27/098 , H01L27/0248 , H01L29/8083 , H03K17/0822 , H03K17/6877
摘要： The invention relates to a semiconductor arrangement, comprising a first depletion layer field effect transistor and a second first depletion layer field effect transistor, wherein each depletion layer field effect transistor comprises a semiconductor body (116) of the one conductor type, which is in contact with a source electrode (S1; S2) and a drain electrode (D) spaced from the same such that between the source electrode and the drain electrode a flow path in created in the semiconductor body, and zones (117, 139, 122; 140, 128, 124) of the other conductor type that is opposite from the one conductor type, wherein the zones are provided in the region of the flow path in the semiconductor body and are in contact with a gate electrode (G1; G2) and form space charge regions controlling the flow path in the semiconductor body (116). The drain electrodes of the two depletion layer field effect transistors are short-circuited, and the source electrode (S1) of the first field effect transistor is short circuited with the gate electrode (G2) of the second depletion layer field effect transistor. The invention further relates to a circuit arrangement comprising this semiconductor arrangement, which has a switch element (104) that is controlled by the potential of the source electrode (S2) of the second depletion layer field effect transistor. The switch element can connect the gate electrode (G1) and the source electrode (S1) of the first depletion layer field effect transistor with a potential difference increasing the space charge regions.

5. 发明公开

EP1961120A4 METHOD OF PRODUCING AND OPERATING A LOW POWER JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：方法生产和经营的阻隔 - 场效应晶体管低功耗
公开(公告)号：EP1961120A4
公开(公告)日：2008-12-31
申请号：EP06844945
申请日：2006-12-07
申请人： DSM SOLUTIONS INC
发明人： KAPOOR ASHOK KUMAR
IPC分类号： H03K19/0175
CPC分类号： H03K19/0941 , H01L27/098 , H01L29/66901 , H01L29/808 , H03K2217/0018
摘要： A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

6. 发明公开

EP1656721A4 INTEGRATED ELECTRONIC DISCONNECTING CIRCUITS METHODS, AND SYSTEMS 审中-公开
标题翻译：方法及系统集成电路电子版
公开(公告)号：EP1656721A4
公开(公告)日：2008-05-07
申请号：EP04761154
申请日：2004-08-20
申请人： FULTEC PTY LTD
发明人： HARRIS RICHARD ALLEN , LINEWIH HANDOKO
IPC分类号： H02H9/02 , H01L27/098 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/808 , H02H9/04
CPC分类号： H01L29/1095 , H01L27/098 , H01L29/0657 , H01L29/0696 , H01L29/0847 , H01L29/7802 , H01L29/7827 , H01L29/8083
摘要： Merged devices for transient blocking. A pass transistor is placed so that its body potential drives the gate of a depletion-mode JFET-type blocking transistor. Thus a transient which appears on an external terminal is very rapidly propagated to shut off the blocking transistor, before large numbers of carriers can be injected. Preferably a shunt device is also used to drop high potentials which may appear at the same time. This connection can be particularly useful in power or data input terminals.

7. 发明授权

EP1673671B1 POWER SYSTEM INHIBIT METHOD AND DEVICE AND STRUCTURE THEREFOR 有权
标题翻译：电力系统LOCK程序和设置及其结构
公开(公告)号：EP1673671B1
公开(公告)日：2008-03-05
申请号：EP04783516.0
申请日：2004-09-10
申请人： Semiconductor Components Industries, LLC
发明人： HALAMIK, Josef , HALL, Jefferson, W.
IPC分类号： G05F3/16 , H01L29/78
CPC分类号： H01L21/823418 , H01L27/0203 , H01L27/0285 , H01L27/088 , H01L27/098 , H03K17/082
摘要： A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23, 24).

8. 发明公开

EP1843470A1 Power system inhibit method and device and structure therefor 有权
标题翻译： Leistungssystem-Sperrverfahren und -Einrichtung und Strukturdafür
公开(公告)号：EP1843470A1
公开(公告)日：2007-10-10
申请号：EP07013802.9
申请日：2004-09-10
申请人： Semiconductor Components Industries, LLC
发明人： Halamik, Josef , Hall, Jefferson W.
IPC分类号： H03K17/082 , G05F3/26
CPC分类号： H01L21/823418 , H01L27/0203 , H01L27/0285 , H01L27/088 , H01L27/098 , H03K17/082
摘要： A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23,24).
摘要翻译：功率控制系统（25）使用两个单独的电流来控制功率控制系统（25）的启动操作。两个电流被分流到地，以禁止功率控制系统（25）的操作，并且禁用两个电流中的一个以最小化功率耗散。响应于两个分离的控制信号（23,24），两个独立控制的电流由多输出电流高压装置（12）产生。

9. 发明授权

EP0225716B1 Non-saturated current semiconductor device having two current paths 失效
标题翻译：具有两个电流条件的非饱和电流半导体器件
公开(公告)号：EP0225716B1
公开(公告)日：1992-07-08
申请号：EP86308406.7
申请日：1986-10-29
申请人： Research Development Corporation of Japan , Barsony, Istvan
发明人： Barsony, Istvan
IPC分类号： H01L29/76
CPC分类号： H01L29/7722 , H01L27/098

10. 发明公开

EP0278410A1 A manufacturing method for cascoded junction type field effect transistors 失效
标题翻译： HerstellungsmethodefürJunction-Feldeffekttransistoren在Kaskodenschaltung。
公开(公告)号：EP0278410A1
公开(公告)日：1988-08-17
申请号：EP88101652.1
申请日：1988-02-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Okano, Jun-ichi Patent Division , Matsumoto, Kiyohito Patent Division
IPC分类号： H01L27/08 , H01L27/06
CPC分类号： H01L27/098 , H01L21/82 , Y10S438/911
摘要： A method for manufacturing cascoded junction type field effect transistors comprises the steps of forming an epitaxial layer (33) of a first conductivity type used as a channel region on a semiconductor substrate (32) of a second conductivity type and performing selective oxidation to form a thick oxide film on part of the epitaxial layer (33). Then, the thick oxide film is removed to provide a part of the surface which is a level lower than the main surface of the epitaxial layer (33). Next, an impurity of the first conductivity type is doped into the low and high surface areas of the epitaxial layer (33) from the surface thereof to form source and drain regions (38 and 39) separated at a preset distance. After this, an impurity of the second conductivity type is doped into the low and high level surface areas of the epitaxial layer (33) between the source and drain regions (38 and 39) to simultaneously form first and second junction gates (44 and 45) which are separated at a present distance. Then, the semiconductor substrate (32) is connected to the second junction gate (45) and source region (38) to connect two junction FETs in cascode fashion.
摘要翻译：制造级联结型场效应晶体管的方法包括以下步骤：在第二导电类型的半导体衬底（32）上形成用作沟道区的第一导电类型的外延层（33），并执行选择性氧化以形成部分外延层（33）上的厚氧化膜。然后，去除厚的氧化物膜以提供比外延层（33）的主表面低的水平的一部分表面。接下来，从其表面将第一导电类型的杂质掺杂到外延层（33）的低表面和高表面区域中，以形成以预设距离分离的源区和漏区（38和39）。此后，第二导电类型的杂质被掺杂到源区和漏区（38和39）之间的外延层（33）的低和高电平表面区域中，以同时形成第一和第二结栅（44和45 ），它们以目前的距离分离。然后，半导体衬底（32）连接到第二结栅极（45）和源极区域（38），以串联方式连接两个结型FET。

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