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1. 发明公开

EP3252827A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：EP3252827A1
公开(公告)日：2017-12-06
申请号：EP17173729.9
申请日：2017-05-31
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： ZHOU, Fei
IPC分类号： H01L29/66 , H01L29/78 , H01L27/092
CPC分类号： H01L27/0924 , H01L21/0332 , H01L21/0337 , H01L21/28035 , H01L21/31111 , H01L21/31144 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L27/0922 , H01L29/0649 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/4916 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： The present invention provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first insulator layer; a second insulator layer covering the fin; a plurality of pseudo gate structures on the second insulator layer, where each pseudo gate structure wraps a part of the fin, where each pseudo gate structure includes a pseudo gate located on the second insulator layer, the plurality of pseudo gate structures includes at least a first pseudo gate structure and a second pseudo gate structure that are spaced from each other, the second pseudo gate structure is located at an edge corner of the fin, and a part of the second pseudo gate structure is on the first insulator layer; spacers, on the first insulator layer and the second insulator layer, at two sides of each of the plurality of pseudo gate structures; and a source or a drain located among the plurality of pseudo gate structures. The present invention can improve reliability of the device.
摘要翻译：本发明提供了一种半导体器件及其制造方法。该器件可以包括：半导体衬底; 从半导体衬底突出的鳍片，其中沟槽形成在鳍片的侧面上; 部分地填充沟槽的第一绝缘体层，其中鳍状物从第一绝缘体层突出; 覆盖所述鳍状物的第二绝缘体层; 在所述第二绝缘层上的多个伪栅极结构，其中每个伪栅极结构包裹所述鳍的一部分，其中每个伪栅极结构包括位于所述第二绝缘层上的伪栅极，所述多个伪栅极结构包括至少一个第一伪栅极结构和第二伪栅极结构，所述第二伪栅极结构位于所述鳍片的边角，所述第二伪栅极结构的一部分位于所述第一绝缘层上; 在所述多个伪栅极结构中的每一个的两侧处的所述第一绝缘体层和所述第二绝缘体层上的间隔体; 以及位于多个伪栅极结构之间的源极或漏极。本发明可以提高设备的可靠性。

2. 发明公开

EP3252826A1 METHOD AND DEVICE FOR COMPOUND SEMICONDUCTOR FIN STRUCTURE 审中-公开
标题翻译：用于复合半导体鳍结构的方法和装置
公开(公告)号：EP3252826A1
公开(公告)日：2017-12-06
申请号：EP17173727.3
申请日：2017-05-31
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： ZHANG, Hai Yang , WANG, Yan
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/6681 , H01L21/3065 , H01L29/0649 , H01L29/1033 , H01L29/161 , H01L29/20 , H01L29/66522 , H01L29/6653 , H01L29/66553 , H01L29/66787 , H01L29/785
摘要： A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer. The first and second semiconductor layers have the same semiconductor compound. The fin structure according to the novel method includes one or more insulator layers to achieve a higher on current/off current ratio, thereby improving the device performance relative to conventional fin structures without the insulator layers.
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成第一半导体层;在第一半导体层上形成半导体层结构的堆叠;以及刻蚀堆叠以形成鳍状结构。每个半导体层结构包括在第一绝缘层上的第一绝缘层和第二半导体层。第一和第二半导体层具有相同的半导体化合物。根据新颖方法的鳍状结构包括一个或多个绝缘体层以实现较高的电流/关断电流比，由此相对于没有绝缘体层的传统鳍结构提高了器件性能。

3. 发明公开

EP3087603A4 HIGH MOBILITY TRANSISTORS 审中-公开
标题翻译： TRANSISTOREN MIT HOHERMOBILITÄT
公开(公告)号：EP3087603A4
公开(公告)日：2017-08-30
申请号：EP14875258
申请日：2014-12-29
申请人： TEXAS INSTRUMENTS INC
发明人： NIIMI HIROAKI , MEHROTRA MANOJ , WISE RICK L
IPC分类号： H01L27/092 , B82Y40/00 , H01L21/8238 , H01L29/10
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/20
摘要： An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.
摘要翻译：包含n沟道finFET和p沟道finFET的集成电路在硅衬底上具有电介质层。 finFET的鳍具有比硅更高的迁移率的半导体材料。 n沟道finFET的鳍片位于穿过衬底上的介电层的第一沟槽中的第一硅锗缓冲器上。 p沟道finFET的鳍片位于穿过衬底上的电介质层的第二沟槽中的第二硅锗缓冲器上。鳍片在介电层上延伸至少10纳米。通过在电介质层中的沟槽中的硅锗缓冲器上外延生长来形成鳍，接着进行CMP平坦化直到电介质层。介电层凹陷以暴露鳍片。翅片可以同时形成或分开形成。

4. 发明公开

EP3087616A4 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURES ON DISSIMILAR SUBSTRATES 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG VON HALBLEITERSTRUKTUREN AUF UNGLEICHEN SUBSTRATEN
公开(公告)号：EP3087616A4
公开(公告)日：2017-08-02
申请号：EP13900449
申请日：2013-12-23
申请人： INTEL CORP
发明人： CHU-KUNG BENJAMIN , TAFT SHERRY R , LE VAN H , DASGUPTA SANSAPTAK , SUNG SEUNG HOON HOON , GARDNER SANAZ K , METZ MATTHEW V , RADOSAVLJEVIC MARKO , THEN HAN WUI
IPC分类号： H01L33/00
CPC分类号： H01L29/1037 , H01L29/0649 , H01L29/161 , H01L29/2003 , H01L29/66795
摘要： Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.
摘要翻译：公开了用于在具有多深宽比掩模的不同衬底上形成无缺陷半导体结构的技术。多深宽比掩模包括在衬底上形成的第一，第二和第三层。第二层具有分别比第一层和第三层中的第一开口和第三开口更宽的第二开口。所有三个开口都沿共同的中心轴居中。半导体材料从衬底的顶表面生长并横向地在第二开口内的第一层的顶表面上生长。通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内和垂直下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

5. 发明公开

EP3036769A4 IMPROVED SILICIDE FORMATION BY IMPROVED SIGE FACETING 有权
标题翻译：改进SILICIDFORMIERUNG改良SIGE小面
公开(公告)号：EP3036769A4
公开(公告)日：2017-04-12
申请号：EP14838365
申请日：2014-08-22
申请人： TEXAS INSTRUMENTS INC
发明人： EKBOTE SHASHANK S , LIM KWAN-YONG , ESHUN EBENEZER , CHOI YOUNSUNG
IPC分类号： H01L27/088 , H01L21/28 , H01L21/336 , H01L29/165
CPC分类号： H01L29/45 , H01L21/28123 , H01L21/823412 , H01L21/823425 , H01L21/823443 , H01L27/0207 , H01L27/088 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41725 , H01L29/458 , H01L29/665 , H01L29/66636 , H01L29/7848

6. 发明公开

EP3041036A4 METHOD FOR MANUFACTURING INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES BIPOLAREN TRANSISTORS MIT ISOLIERTEM GATE
公开(公告)号：EP3041036A4
公开(公告)日：2017-01-25
申请号：EP14839057
申请日：2014-08-25
申请人： CSMC TECHNOLOGIES FAB1 CO LTD
发明人： ZHONG SHENGRONG , ZHOU DONGFEI , DENG XIAOSHE , WANG GENYI
IPC分类号： H01L21/331 , H01L29/06 , H01L29/10 , H01L29/739
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/045 , H01L29/0619 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/401 , H01L29/407 , H01L29/408 , H01L29/66333 , H01L29/6634 , H01L29/7395 , H01L29/7396
摘要： A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a poly silicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.
摘要翻译：一种绝缘栅双极型晶体管（100）的制造方法，其特征在于，在基板（10）的前表面形成基板（10），形成场氧化物层（20），形成端子保护环（23）。通过使用有源区光掩模对有源区域氧化物层（20）进行光刻和蚀刻，通过使用光致抗蚀剂作为掩模膜将N型离子引入到衬底（10）中; 在所述场氧化物层（20）的蚀刻衬底（10）上沉积和形成多晶硅栅极（31），并在所述多晶硅栅极（31）上形成保护层; 在N型离子的导入区域上进行接合，然后形成载流子增强区域（41）。通过使用P阱光掩模进行光蚀刻，将P型离子引入载体增强区域（41）中，并进行结合推压然后形成P体区域; 通过多晶硅栅极进行N型离子的自对准引入到P-体区域，并进行结压并形成N型重掺杂区域; 在所述多晶硅栅极的两侧形成侧壁，将P型离子引入所述N型重掺杂区域中，并执行结推进然后形成P型重掺杂区域; 并去除保护层，然后进行多晶硅栅极的引入和掺杂。该方法减少了设置载流子增强区域的正向压降。

7. 发明公开

EP3087616A1 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURES ON DISSIMILAR SUBSTRATES 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG VON HALBLEITERSTRUKTUREN AUF UNGLEICHEN SUBSTRATEN
公开(公告)号：EP3087616A1
公开(公告)日：2016-11-02
申请号：EP13900449.3
申请日：2013-12-23
申请人： Intel Corporation
发明人： CHU-KUNG, Benjamin , TAFT, Sherry R. , LE, Van H. , DASGUPTA, Sansaptak , SUNG, Seung Hoon Hoon , GARDNER, Sanaz K. , METZ, Matthew V. , RADOSAVLJEVIC, Marko , THEN, Han Wui
IPC分类号： H01L33/00
CPC分类号： H01L29/1037 , H01L29/0649 , H01L29/161 , H01L29/2003 , H01L29/66795
摘要： Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.
摘要翻译：公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。多纵横比掩模包括在基底上形成的第一，第二和第三层。第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。所有三个开口沿着共同的中心轴线居中。半导体材料从衬底的顶表面生长并在第二开口内侧向生长到第一层的顶表面上。通过使用第三层作为蚀刻掩模蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。

8. 发明公开

EP3087603A1 HIGH MOBILITY TRANSISTORS 审中-公开
标题翻译：高移动性晶体管
公开(公告)号：EP3087603A1
公开(公告)日：2016-11-02
申请号：EP14875258.7
申请日：2014-12-29
申请人： Texas Instruments Incorporated
发明人： NIIMI, Hiroaki , MEHROTRA, Manoj , WISE, Rick, L.
IPC分类号： H01L27/092 , H01L21/8238 , B82Y40/00
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0684 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/20
摘要： An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.
摘要翻译：包含n沟道finFET（106）和p沟道finFET（110）的集成电路（100）在硅衬底（102）上具有介电层（112）。 finFET（106,110）的鳍具有比硅具有更高迁移率的半导体材料。 n沟道finFET（106）的鳍片位于穿过衬底（102）上的介电层（112）的第一沟槽（114）中的第一硅锗缓冲器（118）上。 p沟道finFET（110）的鳍状物在穿过衬底（102）上的电介质层（112）的第二沟槽（116）中的第二硅锗缓冲器（132）上。鳍片在电介质层（112）上方延伸至少10纳米。通过在电介质层（112）中的沟槽（114,116）中的硅锗缓冲区（118,132）上外延生长来形成鳍，接着进行CMP平坦化直到电介质层（112）。介电层（112）凹陷以暴露鳍片。翅片可以同时形成或分开形成。

9. 发明公开

EP3084812A1 NMOS AND PMOS STRAINED DEVICES WITHOUT RELAXED SUBSTRATES 审中-公开
标题翻译： NMOS-UND PMOS-VORGESPANNTE VORRICHTUNGEN OHNE柔性基板
公开(公告)号：EP3084812A1
公开(公告)日：2016-10-26
申请号：EP13899638.4
申请日：2013-12-16
申请人： Intel Corporation
发明人： CEA, Stephen M. , KOTLYAR, Roza , KENNEL, Harold W. , MURTHY, Anand S. , GLASS, Glenn A. , KUHN, Kelin J. , GHANI, Tahir
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/045 , H01L29/161 , H01L29/165 , H01L29/66431 , H01L29/66818 , H01L29/7781 , H01L29/7782
摘要： Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor.
摘要翻译：与没有松弛基板的应变NMOS和PMOS器件有关的技术和方法，以及这样的半导体器件的系统及其方法。

10. 发明公开

EP2920815A4 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 有权
标题翻译：隧道场效应晶体管（TFET）FOR CMOS建筑与PROCESS FOR N型和P型PRODUCING TFET
公开(公告)号：EP2920815A4
公开(公告)日：2016-10-12
申请号：EP13854345
申请日：2013-06-12
申请人： INTEL CORP
发明人： KOTLYAR ROZA , CEA STEPHEN M , DEWEY GILBERT , CHU-KUNG BENJAMIN , AVCI UYGAR E , RIOS RAFAEL , CHAUDHRY ANURAG , LINTON JR THOMAS D , YOUNG IAN A , KUHN KELIN J
IPC分类号： H01L29/78 , H01L21/336 , H01L29/739
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696

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