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1. 发明公开

EP3306665A3 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
公开(公告)号：EP3306665A3
公开(公告)日：2018-07-18
申请号：EP17195405.0
申请日：2017-10-09
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： LI, Yong
IPC分类号： H01L27/12 , H01L27/092 , H01L21/84 , H01L21/8238
CPC分类号： H01L27/0886 , H01L21/0276 , H01L21/3083 , H01L21/31116 , H01L21/31144 , H01L21/762 , H01L21/8238 , H01L21/823814 , H01L21/823821 , H01L21/823864 , H01L21/823878 , H01L21/823892 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L27/12 , H01L27/1207 , H01L27/1211 , H01L29/66818
摘要： A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a plurality of fins on a substrate including an NMOS region and a PMOS region adjacent to the NMOS region; forming an N-type well in the PMOS region and a P-type well in the NMOS region of the substrate; forming a protective sidewall to cover an upper portion of a sidewall surface of each fin in each of the NMOS region and PMOS region and to expose a lower portion of the sidewall surface of each fin; removing a partial width of the lower portion of the fin using the protective sidewall as an etch mask; removing the protective sidewall; and forming an isolation structure at least by oxidizing the remaining lower portion of the fin and having a top surface lower than the neighboring upper portions of the fins.

2. 发明公开

EP3314661A1 SUB-FIN SIDEWALL PASSIVATION IN REPLACEMENT CHANNEL FINFETS 审中-公开
标题翻译：替换通道鳍片中的子鳍侧壁钝化
公开(公告)号：EP3314661A1
公开(公告)日：2018-05-02
申请号：EP15896512.9
申请日：2015-06-24
申请人： Intel Corporation
发明人： GLASS, Glenn A. , PANG, Ying , MURTHY, Anand S. , GHANI, Tahir , JAMBUNATHAN, Karthik
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/408 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1054 , H01L29/16 , H01L29/20 , H01L29/42392 , H01L29/6681 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

3. 发明公开

EP3312876A1 FINFET DEVICE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： FINFET器件及其制造方法
公开(公告)号：EP3312876A1
公开(公告)日：2018-04-25
申请号：EP17196528.8
申请日：2017-10-16
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： LI, Yong
IPC分类号： H01L21/8238 , H01L21/225 , H01L29/66 , H01L29/78 , H01L27/092
CPC分类号： H01L21/823821 , H01L21/2254 , H01L21/2255 , H01L21/823814 , H01L21/823878 , H01L27/0924 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/785
摘要： A FinFET device and fabrication method thereof is provided. The fabrication method includes: providing a semiconductor substrate (101) with a fin (102) protruding from the semiconductor substrate, and a gate structure (110) across a length portion of the fin and covering a portion of the fin; etching a partial thickness of the fin on both sides of the gate structure to form grooves (201); forming a doped layer (211) in a bottom and sidewalls of the grooves; annealing the doped layer to allow the doping ions to diffuse into the fin and to form a lightly doped source/drain region (221); removing the doped layer after the annealing; and forming epitaxial layers to fill up the grooves.
摘要翻译：提供FinFET器件及其制造方法。所述制造方法包括：提供具有从所述半导体衬底突出的鳍状物（102）的半导体衬底（101）以及跨越所述鳍状物的长度部分并覆盖所述鳍状物的一部分的栅极结构（110）; 在所述栅极结构的两侧蚀刻所述鳍的部分厚度以形成凹槽（201）; 在槽的底部和侧壁中形成掺杂层（211）退火掺杂层以允许掺杂离子扩散到鳍中并形成轻掺杂源极/漏极区（221）; 在退火之后去除掺杂层; 并形成外延层以填充沟槽。

5. 发明公开

EP3084815A4 SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME 审中-公开
公开(公告)号：EP3084815A4
公开(公告)日：2018-01-03
申请号：EP13899890
申请日：2013-12-19
申请人： INTEL CORP
发明人： WEBB MILTON CLAIR , BOHR MARK , GHANI TAHIR , LIAO SZUYA S
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0649 , H01L21/76895 , H01L21/823821 , H01L21/823878 , H01L23/535 , H01L27/0924 , H01L29/41791 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

6. 发明公开

EP3120388A4 TECHNIQUES FOR INTEGRATION OF GE-RICH P-MOS SOURCE/DRAIN CONTACTS 审中-公开
公开(公告)号：EP3120388A4
公开(公告)日：2017-11-29
申请号：EP14886485
申请日：2014-03-21
申请人： INTEL CORP
发明人： GLASS GLENN A , MURTHY ANAND S , GHANI TAHIR , PANG YING , MISTKAWI NABIL G
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L29/161
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/02532 , H01L21/30604 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0649 , H01L29/0673 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

7. 发明公开

EP3242320A1 FINFET AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：鳍式场效应晶体管及其制造方法
公开(公告)号：EP3242320A1
公开(公告)日：2017-11-08
申请号：EP17168684.3
申请日：2017-04-28
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： LI, Yong
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/30604 , H01L21/3081 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A method is provided for fabricating a FinFET. The method includes providing a substrate including an NMOS region; forming a plurality of fins on the substrate; forming an isolation layer between adjacent fins and on the substrate; forming a gate structure across a length portion of the fin; forming a first mask layer on the top surface and sidewalls of the fin; etching the first mask layer to expose the top surface of the fin on both sides of the gate structure; removing a thickness portion of the fin on both sides of the gate structure, wherein the etched fin and the remaining first mask layer form a first trench; performing a thinning treatment of the remaining first mask layer on a sidewall of the first trench to increase width of the first trench; and forming an N-type in-situ doped epitaxial layer to fill up the first trench.
摘要翻译：提供了一种制造FinFET的方法。该方法包括提供包括NMOS区域的衬底; 在衬底上形成多个翅片; 在相邻的鳍片之间和衬底上形成隔离层; 在鳍的长度部分上形成栅极结构; 在鳍的顶面和侧壁上形成第一掩模层; 刻蚀所述第一掩模层以暴露所述栅极结构两侧上的所述鳍的顶表面; 去除所述栅极结构两侧的所述鳍片的厚度部分，其中所述经蚀刻的鳍片和所述剩余的第一掩模层形成第一沟槽; 对所述第一沟槽的侧壁上的剩余的第一掩模层执行减薄处理以增加所述第一沟槽的宽度; 以及形成N型原位掺杂外延层以填充第一沟槽。

8. 发明公开

EP3193374A4 COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR 有权
标题翻译： KOMPLEMENTÄRERTUNNELFELDEFFEKTTRANSISTOR UND HERSTELLUNGSVERFAHRENDAFÜR
公开(公告)号：EP3193374A4
公开(公告)日：2017-08-23
申请号：EP15857108
申请日：2015-04-27
申请人： HUAWEI TECH CO LTD
发明人： YANG XICHAO , ZHAO JING , ZHANG CHEN-XIONG
IPC分类号： H01L29/78 , H01L21/336 , H01L27/082 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/739
CPC分类号： H01L29/66977 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823878 , H01L21/823885 , H01L27/092 , H01L29/0653 , H01L29/0676 , H01L29/08 , H01L29/42356 , H01L29/42392 , H01L29/4908 , H01L29/66356 , H01L29/7391 , H01L29/78 , H01L29/78618 , H01L29/78642 , H01L29/78651 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： Embodiments of the present invention provide a complementary tunneling field effect transistor and a manufacturing method therefor, which relate to the field of semiconductor technologies. The complementary tunneling field effect transistor can increase carrier tunneling efficiency and improve performance of the complementary tunneling field effect transistor. The transistor includes: a first drain region (20a) and a first source region (20b) that are disposed on a substrate (10), where the first drain region and the first source region include a first dopant; a first channel (30a) that is disposed on the first drain region and a second channel (30b) that is disposed on the first source region; a second source region (40a) that is disposed on the first channel and a second drain region (40b) that is disposed on the second channel, where the second source region and the second drain region include a second dopant; a first epitaxial layer (50a) that is disposed on the first drain region and the second source region, and a second epitaxial layer (50b) that is disposed on the second drain region and the first source region; and a first gate stack layer (60a) that is disposed on the first epitaxial layer, and a second gate stack layer (60b) that is disposed on the second epitaxial layer.
摘要翻译：本发明的实施例提供一种互补隧穿场效应晶体管及其制造方法，涉及半导体技术领域。互补隧穿场效应晶体管可以提高载流子隧穿效率并提高互补隧道场效应晶体管的性能。晶体管包括：设置在衬底（10）上的第一漏极区（20a）和第一源极区（20b），其中第一漏极区和第一源极区包括第一掺杂剂; 设置在第一漏极区上的第一沟道（30a）和设置在第一源极区上的第二沟道（30b）; 设置在所述第一沟道上的第二源极区域（40a）和设置在所述第二沟道上的第二漏极区域（40b），其中所述第二源极区域和所述第二漏极区域包括第二掺杂剂; 设置在所述第一漏极区域和所述第二源极区域上的第一外延层（50a）以及设置在所述第二漏极区域和所述第一源极区域上的第二外延层（50b）以及设置在第一外延层上的第一栅堆叠层（60a）以及设置在第二外延层上的第二栅堆叠层（60b）。

9. 发明公开

EP3176816A1 WELL IMPLANTATION PROCESS FOR FINFET DEVICE 审中-公开
标题翻译： FINFET器件的良好注入工艺
公开(公告)号：EP3176816A1
公开(公告)日：2017-06-07
申请号：EP16199529.5
申请日：2016-11-18
申请人： Semiconductor Manufacturing International Corporation (Beijing) , Semiconductor Manufacturing International Corporation (Shanghai)
发明人： ZHOU, Fei
IPC分类号： H01L21/8238 , H01L29/66
CPC分类号： H01L21/823892 , H01L21/26513 , H01L21/823493 , H01L21/823821 , H01L21/823878 , H01L27/0925 , H01L27/0927 , H01L27/0928 , H01L29/66803
摘要： A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.
摘要翻译：一种用于制造半导体器件的方法包括提供衬底，在衬底的第一区域中执行N型掺杂剂注入以形成N阱，去除衬底的一部分以在N阱上形成第一组鳍片，以及邻近所述N阱的所述衬底的第二区域上的第二组鳍片，填充所述鳍片之间的间隙空间以形成隔离区域，以及向所述第二区域中执行P型掺杂剂注入以形成P阱毗邻N井。 N阱和P阱分别在不同的时间形成。由于P型掺杂剂离子在P阱中扩散到隔离区中而导致的P型掺杂剂离子的损失可以被消除，并且可以避免由N型掺杂剂离子引起的对鳍片的损伤。

10. 发明公开

EP3050092A4 NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND CONFORMAL EPITAXY 审中-公开
标题翻译：之间。通过组合选择性，符合外延在硅衬底EYED FOR CMOS硅-FREE装置的各层
公开(公告)号：EP3050092A4
公开(公告)日：2017-05-03
申请号：EP13894917
申请日：2013-09-27
申请人： INTEL CORP
发明人： GOEL NITI , CHAU ROBERT S , KAVALIEROS JACK T , CHU-KUNG BENJAMIN , METZ MATTHEW V , MUKHERJEE NILOY , ZELICK NANCY M , DEWEY GILBERT , RACHMADY WILLY , RADOSAVLJEVIC MARKO , LE VAN H , PILLARISETTY RAVI , DASGUPTA SANSAPTAK
IPC分类号： H01L21/336 , H01L21/02 , H01L21/20 , H01L21/8238 , H01L21/8252 , H01L27/092 , H01L29/06 , H01L29/165 , H01L29/205 , H01L29/66 , H01L29/78
CPC分类号： H01L21/0245 , H01L21/02381 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/02598 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L21/8252 , H01L27/0922 , H01L27/0924 , H01L29/0649 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66795 , H01L29/785
摘要： A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
摘要翻译：单鳍或一对的共整合n型和p型单晶电子装置翅片外延从表面基材在一个的底部或一对浅沟槽隔离（STI）区域之间形成的沟槽的生长。翅片或散热片被图案化和STI区域被蚀刻以形成上述的STI区的蚀刻顶表面延伸的翅片或翼片的高度。翅片高度可以是至少1.5倍的宽度。暴露的侧壁表面和每个翅片的顶表面上外延与一种或多种适形外延材料包覆，以形成在鳍的器件层。之前生长翅片，毯子缓冲外延材料可从表面衬底上生长; 和在STI生长翅片沟槽的覆盖层的上方形成。翅片的搜索形成降低从材料界面的晶格失配的缺陷。

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