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21. 发明公开

EP0435541A3 Semiconductor device having internal current limit overvoltage protection 失效
标题翻译：具有内部电流限制保护功能的半导体器件
公开(公告)号：EP0435541A3
公开(公告)日：1991-07-31
申请号：EP90313775.0
申请日：1990-12-17
申请人： MOTOROLA, INC.
发明人： Masquelier, Michael P. , Okada, David N.
IPC分类号： H01L29/73 , H01L29/06 , H01L29/10
CPC分类号： H01L29/1004 , H01L29/1008 , H01L29/36 , H01L29/7322 , H01L29/735 , Y10S148/011
摘要： A semiconductor device having internally limited current and overvoltage protection is disclosed and comprises having at least a first junction (40,96) wherein both sides of the junction (40,96) have predetermined dopant concentrations and wherein the first junction (40,96) is spaced apart a predetermined distance from either a second junction (42) or current blocking means (108). The predetermined dopant concentrations and distance are such that when a predetermined voltage is applied to the device (10,82), a depletion region (44, 110) from the first junction (40,96) encounters either a depletion region (44) from the second junction (42) or current blocking means (108), thereby pinching-off current at a desired voltage. The pinch-off voltage may be varied by adjusting the distance between the first junction (40,96) and either the second junction (42) or current blocking means (108) and also by adjusting the predetermined dopant concentrations.

22. 发明公开

EP0247386A3 Lateral transistor 失效
标题翻译：横向晶体管
公开(公告)号：EP0247386A3
公开(公告)日：1988-03-16
申请号：EP87106346
申请日：1987-05-02
申请人： TELEFUNKEN electronic GmbH
发明人： Arndt, Jürgen, Dr.
IPC分类号： H01L29/72 , H01L27/06 , H01L21/82 , H01L29/10
CPC分类号： H01L29/402 , H01L21/2652 , H01L21/74 , H01L21/8249 , H01L29/1008 , H01L29/735 , Y10S148/009 , Y10S148/01

23. 发明公开

EP0060761A1 Transistor bipolaire latéral sur isolant et son procédé de fabrication 失效
标题翻译：侧向双极晶体管隔离器和Verfahren zu seiner Herstellung。
公开(公告)号：EP0060761A1
公开(公告)日：1982-09-22
申请号：EP82400388.3
申请日：1982-03-05
申请人： SOCIETE POUR L'ETUDE ET LA FABRICATION DE CIRCUITS INTEGRES SPECIAUX - E.F.C.I.S.
发明人： Mackowiak, Eugène , Borel, Joseph , Montier, Michel
IPC分类号： H01L29/72 , H01L29/10 , H01L29/60 , H01L29/62 , H01L21/285
CPC分类号： H01L29/66265 , H01L29/1008 , H01L29/42304 , H01L29/7317
摘要： L'invention concerne un transistor bipolaire NPN ou PNP réalisé selon une disposition latérale sur un substrat isolant (10).
Ce transistor comprend côte à côte une région d'émetteur (12), une région de base étroite (20) et une région de collecteur (14), toutes trois en silicium monocristallin, avec une couche de silicium polycristallin étroite (22) recouvrant exactement la région étroite de base et servant de conducteur d'accès à cette région. Un contact métallique est relié à cette région de silicium polycristallin, mais en dehors de la zone de base proprement dite entre l'émetteur et le collecteur, afin de ne pas risquer un court-circuit des jonctions par la métallisation. Ce transistor bipolaire est réalisable selon une technologie MOS.
摘要翻译： 1.一种绝缘层上的横向双极晶体管，包括： - 绝缘衬底（10）， - 由第一导电类型的掺杂硅制成的发射极区域（12）， - 由掺杂的硅制成的集电极区域（14）第一导电类型与第一导电类型分离，窄间隔， - 第二导电类型的掺杂硅的基极区域，在发射极和集电极区域之间的狭窄空间中延伸，发射极和集电极接触区域分别在发射极区域和集电极区域的硅上的金属沉积物（16,18）， - 与基底区域相邻的发射极和集电极区域的部分之上的氧化硅绝缘层（15），其特征在于 - 绝缘体层在基区之上呈现中断， - 掺杂有第二导电类型的杂质的低电阻率的多晶硅（22）的区域以窄带的形式延伸到基部区域上，该窄带可部分地在所述绝缘层上方并且与基底区域接触并且具有延伸超过发射器（12）和收集器区域（14）的终端区域（22），从而允许建立金属接触件（26），从而使该多晶硅硅片面积。

24. 发明授权

EP4070384B1 A TRANSISTOR DEVICE 有权
公开(公告)号：EP4070384B1
公开(公告)日：2024-04-17
申请号：EP21830472.3
申请日：2021-12-09
IPC分类号： H01L27/06 , H01L27/082 , H01L29/06 , H01L29/10 , H01L29/735 , H01L27/098 , H01L29/66 , H01L29/808
CPC分类号： H01L29/808 , H01L29/735 , H01L27/098 , H01L27/082 , H01L27/0623 , H01L29/0692 , H01L29/1008 , H01L29/6625

25. 发明授权

EP2784823B1 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：EP2784823B1
公开(公告)日：2018-05-23
申请号：EP14168446.4
申请日：2008-12-19
申请人： Asahi Kasei EMD Corporation
发明人： Koricic, Marko , Suligoj, Tomislav , Mochizuki, Hidenori , Morita, Soichi
IPC分类号： H01L29/735 , H01L21/331 , H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/08 , H01L29/10 , H01L21/265
CPC分类号： H01L27/0623 , H01L21/2257 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/8249 , H01L29/0808 , H01L29/1008 , H01L29/1045 , H01L29/6625 , H01L29/665 , H01L29/6659 , H01L29/735
摘要： A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.

26. 发明授权

EP2224478B1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权转让
公开(公告)号：EP2224478B1
公开(公告)日：2018-01-24
申请号：EP08865744.0
申请日：2008-12-19
申请人： Asahi Kasei EMD Corporation
发明人： KORICIC, Marko , SULIGOJ, Tomislav , MOCHIZUKI, Hidenori , MORITA, Soichi
IPC分类号： H01L29/735 , H01L21/331 , H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/08 , H01L29/10 , H01L21/265 , H01L21/225
CPC分类号： H01L27/0623 , H01L21/2257 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/8249 , H01L29/0808 , H01L29/1008 , H01L29/1045 , H01L29/6625 , H01L29/665 , H01L29/6659 , H01L29/735
摘要： A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.

27. 发明公开

EP2784823A3 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：EP2784823A3
公开(公告)日：2015-02-25
申请号：EP14168446.4
申请日：2008-12-19
申请人： Asahi Kasei EMD Corporation
发明人： Koricic, Marko , Suligoj, Tomislav , Mochizuki, Hidenori , Morita, Soichi
IPC分类号： H01L29/735 , H01L21/331 , H01L21/8249 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/08 , H01L29/10
CPC分类号： H01L27/0623 , H01L21/2257 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/8249 , H01L29/0808 , H01L29/1008 , H01L29/1045 , H01L29/6625 , H01L29/665 , H01L29/6659 , H01L29/735
摘要： A semiconductor device in which a lateral bipolar transistor and a CMOS transistor are hybrid-integrated, and the lateral bipolar transistor includes an open region opened in a device isolating oxide film surrounding an active region; a polysilicon film formed on the open region; and a protective film covering at least a part of a peripheral surface of the active region exposed by opening the open region in the device isolating oxide film, wherein the polysilicon film has such a thickness as to expose the active region out of the polysilicon film, and the protective film is a film for preventing the active region from being etched when the polysilicon film is etched to the thickness.

28. 发明公开

EP2224478A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICEDISPOSITIF À SEMI-CONDUCTEURRS ET PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEURS 有权转让
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS的HALBLEITERBAUEMENT
公开(公告)号：EP2224478A1
公开(公告)日：2010-09-01
申请号：EP08865744.0
申请日：2008-12-19
申请人： Asahi Kasei EMD Corporation
发明人： KORICIC, Marko , SULIGOJ, Tomislav , MOCHIZUKI, Hidenori , MORITA, Soichi
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/73
CPC分类号： H01L27/0623 , H01L21/2257 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/8249 , H01L29/0808 , H01L29/1008 , H01L29/1045 , H01L29/6625 , H01L29/665 , H01L29/6659 , H01L29/735
摘要： A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT 100 and a CMOS transistor 200 hybrid-integrated therein. The HCBT 100 has an open region 21 opened by etching a device isolating oxide film 6 surrounding an n-hill layer 11, an emitter electrode 31A and a collector electrode 31B each of which is formed in the open region 21 and is composed of a polysilicon film having such a thickness as to expose the n-hill layer 11 exposed by etching the device isolating oxide film, and an ultrathin oxide film 24 covering at least a part of the n-hill layer 11. The ultrathin oxide film 24 functions as a protective film for protecting the n-hill layer 11 from being etched when the polysilicon film is etched to form the emitter electrode 31A and the collector electrode 31B.
摘要翻译：提供了适用于高性能横向晶体管（HCBT）和CMOS晶体管的混合集成（BiCMOS）的横向晶体管的结构以及制造横向晶体管的方法。半导体器件包括混合集成在其中的HCBT 100和CMOS晶体管200。 HCBT 100具有通过蚀刻围绕n-hill层11的器件隔离氧化膜6，发射电极31A和集电极31B而开放的开放区域21，每个形成在开放区域21中并且由多晶硅具有通过蚀刻器件隔离氧化膜而暴露的n-hill层11的厚度的膜和覆盖n-hill层11的至少一部分的超薄氧化膜24.超薄氧化物膜24用作当蚀刻多晶硅膜以形成发射极31A和集电极31B时，用于保护n-hill层11不被蚀刻的保护膜。

29. 发明公开

EP1868234A2 High withstand voltage semiconductor device and manufacturing method thereof 失效
标题翻译：耐高电压半导体器件及其制造方法
公开(公告)号：EP1868234A2
公开(公告)日：2007-12-19
申请号：EP07018406.4
申请日：1996-03-26
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Akiyama, Hajime
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7824 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1008 , H01L29/102 , H01L29/1083 , H01L29/402 , H01L29/41725 , H01L29/66674 , H01L29/7302 , H01L29/7393 , H01L29/7394 , H01L29/7436 , H01L29/7455 , H01L29/7801 , H01L29/7835
摘要： An n - layer (2) is formed on a main surface of a p-type semiconductor substrate (1). A p - diffusion region (5) is formed at a surface of n - layer (2). A p diffusion region (6) is formed contiguous to one end of p - diffusion region (5). A plurality of p diffusion regions (20) containing p-type impurity the concentration of which is higher than that of p - diffusion region (5) are formed in p - diffusion region (5). A p diffusion region (3) is formed such that it is spaced apart from p - diffusion region (5). A gate electrode (9) is formed on a surface of n - layer (2) positioned between p diffusion region (3) and p - diffusion region (5) with an oxide film (10) interposed. A drain electrode (12) is formed in contact with a surface of p diffusion region (6). Furthermore, an n diffusion region (4) is formed adjacent to p diffusion region (3), and a source electrode (11) is formed in contact with both a surface of n diffusion region (4) and a surface p diffusion region (3).

30. 发明公开

EP1253645A2 Lateral transistor having graded base region, semiconductor intergrated circuit and fabrication method thereof 审中-公开
标题翻译：侧向晶体管mit gradierter Basiszone，integrierter Halbleiterschaltkreis unddiesbezüglichesHerstellungsverfahren
公开(公告)号：EP1253645A2
公开(公告)日：2002-10-30
申请号：EP01125651.8
申请日：2001-10-26
申请人： SANKEN ELECTRIC CO., LTD.
发明人： Yamamoto, Makoto, Sanken Electric Co., Ltd. , Iwabuchi, Akio, Sanken Electric Co., Ltd.
IPC分类号： H01L29/10 , H01L29/735 , H01L21/331
CPC分类号： H01L29/6625 , H01L29/1008 , H01L29/36 , H01L29/735
摘要： The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.
摘要翻译：横向pnp晶体管包括p型半导体衬底，设置在半导体衬底上的n型第一掩埋区域，设置在第一掩埋区域上的n型均匀基极区域，设置在均匀的n型第一插塞区域基极区域，p型第一发射极区域和布置在均匀基极区域的顶表面中的第一集电极区域，设置在均匀基极区域中的渐变基极区域和布置在第一插塞区域中的第一基极接触区域。分级基极区域包围第一主电极区域的底部和侧面。介于第一发射极区域和第一集电极区域之间的渐变基极区域中的掺杂分布使得杂质浓度从第一主电极区域朝向第二主电极区域逐渐减小。

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