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1. 发明公开

EP1583143A3 Method of fabricating self-aligned source and drain contacts in a Double gate FET with controlled manufacturing of a thin Si or non-Si channel 有权转让
标题翻译：用于在受控的生产薄Si或非Si沟道的产生在一个双栅极FET自对准源极/漏极接触方法
公开(公告)号：EP1583143A3
公开(公告)日：2008-06-11
申请号：EP05003842.1
申请日：2005-02-23
申请人： Interuniversitair Microelektronica Centrum , Koninklijke Philips Electronics N.V.
发明人： Ponomarev, Youri V. , Loo, Josine Johanna Gerarda Petra
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/78696 , B82Y10/00 , H01L21/76897 , H01L29/0665 , H01L29/0673 , H01L29/66265 , H01L29/66742 , H01L29/7317 , H01L29/78645
摘要： The invention relates to a method of forming a transistor structure on a substrate (SOI), the substrate comprising a supporting Si layer (1), a buried insulating layer (2), and a top Si layer (3) comprising a high dopant level, the transistor structure comprising a gate region (G1), and a source and drain region (5).
The method further comprises the formation of the gate region (G1) on the top Si layer (3), the gate region (G1) being separated from the top Si layer (3) by a dielectric layer (GD), the formation of an open area (O1) on the top Si layer (3) demarcated by a demarcating oxide and/or resist layer region (4), the formation of high level impurity or heavily-damaged regions (5) by ion implantation, exposing the open area (O1) to an ion beam (IB), with the demarcating layer region (4) and the gate region (G1) acting as implantation mask.
The ion beam (IB) comprises a combination of beam energy and dose, which allows the formation, in the top Si layer (3), of high impurity level regions (L1) below the source and drain regions (5) in the buried insulating layer (2) and of a high impurity level or heavily-damaged regions (L0) below the gate region (G1) in the top Si layer (3).

2. 发明公开

EP1630863A1 Method of fabricating a monolithically integrated vertical semiconducting device in a SOI substrate 有权
标题翻译：韦尔法罕zur Herstellung eines的整体SOI-Substrat
公开(公告)号：EP1630863A1
公开(公告)日：2006-03-01
申请号：EP04020674.0
申请日：2004-08-31
申请人： Infineon Technologies AG
发明人： Johansson, Ted , Norström, Hans
IPC分类号： H01L21/84 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02639 , H01L21/76264 , H01L27/0623 , H01L27/1203 , H01L29/66265
摘要： A method in the fabrication of a monolithically integrated vertical device on an SOI substrate comprises the steps of providing an SOI substrate including, from bottom to top, a silicon bulk material (11), an insulating layer (12), and an monocrystalline silicon layer (13); forming an opening (31) in the substrate, which extends into the bulk material (11), forming silicon oxide on exposed silicon surfaces in the opening and subsequently removing the formed oxide (51), whereby steps (61) in the opening are formed; forming a region (62) of epitaxial silicon in the opening; and forming a deep trench (161) in an area around the opening, whereby the steps (61) in the opening are removed.
摘要翻译：在SOI衬底上制造单片集成垂直器件的方法包括以下步骤：提供SOI衬底，其包括从底部到顶部的硅体材料（11），绝缘层（12）和单晶硅层（13）; 在衬底中形成延伸到体材料（11）中的开口（31），在开口中的暴露的硅表面上形成氧化硅，随后去除所形成的氧化物（51），由此形成开口中的步骤（61） ; 在所述开口中形成外延硅的区域（62）; 以及在开口周围的区域中形成深沟槽（161），从而去除了开口中的台阶（61）。

3. 发明公开

EP1514305A2 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：半导体部件及其制造方法
公开(公告)号：EP1514305A2
公开(公告)日：2005-03-16
申请号：EP03756079.4
申请日：2003-06-02
申请人： Philips Intellectual Property & Standards GmbH , Koninklijke Philips Electronics N.V.
发明人： SCHNITT, WolfgangPhilips Intellectual Property , POHLMANN, Haukec/o Philips Intellectual Property
IPC分类号： H01L21/84 , H01L27/12 , H01L21/762 , H01L29/735
CPC分类号： H01L29/66265 , H01L21/76264 , H01L29/7317
摘要： To refine a semiconductor device (100), in particular a S[ilicon]O[n]I[nsulator] device, comprising: at least one isolating layer (10) made of a dielectric material; at least one silicon substrate (20) arranged on said isolating layer (10); at least one component (30) integrated in the silicon substrate (20), which component has at least one slightly doped zone (34); as well as at least a first, in particular planar, metallization region (40) arranged between the isolating layer (10) and the component (30), in particular between the isolating layer (10) and the slightly doped zone (34) of the component (30), as well as a method of manufacturing at least one semiconductor device (100) in such a manner that trouble-free operation also of slightly doped components (30), such as pnp transistors, is guaranteed in a SOI process transferred onto the insulator, it is proposed that at least a second, in particular planar, metallization region (42) is arranged on the side of the silicon substrate (20) facing away from the isolating layer (10), in the area of the component (30), particularly in the area of the slightly doped zone (34) of the component (30).

4. 发明公开

EP1040517A2 SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD FOR SEMICONDUCTOR COMPONENT 有权
标题翻译：半导体部件及其制造方法
公开(公告)号：EP1040517A2
公开(公告)日：2000-10-04
申请号：EP98954909.2
申请日：1998-11-16
申请人： Telefonaktiebolaget L M Ericsson (Publ)
发明人： SÖDERBÄRG, Anders , SJÖDIN, H kan
IPC分类号： H01L21/763 , H01L21/74 , H01L21/762 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/1203 , H01L29/0821 , H01L29/66772 , H01L29/7809 , Y10S257/904
摘要： A semiconductor comprising a buried conducting layer (108), such as a buried collector, comprises a trench, the walls of which are covered with a layer (109') of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall (109'). The dopants will diffuse through the layer (109') and form a low resistance connection to the buried layer (108). The layer (109') may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer (109') is not in itself conducting, the size of the component may be significantly reduced.

5. 发明公开

EP0632489A2 Herstellungsverfahren für lateralen Bipolartransistor 失效
标题翻译：上述横向双极性晶体管的制造方法。
公开(公告)号：EP0632489A2
公开(公告)日：1995-01-04
申请号：EP94109100.1
申请日：1994-06-14
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Bertagnolli, Emmerich, Dr. , Klose, Helmut, Dr.
IPC分类号： H01L21/331 , H01L29/735
CPC分类号： H01L29/66265 , H01L29/7317 , Y10S148/01
摘要： Verfahren zur Herstellung lateraler Bipolartransistoren auf SOI-Substrat, bei dem in der Siliziumschicht dieses SOI-Substrates eine Grunddotierung für den Leitfähigkeitstyp von Emitter und Kollektor hergestellt wird, außerhalb des für den Transistor vorgesehenen Bereiches Isolationsbereiche (5) hergestellt werden, Kontaktschichten (71, 81) und Dielektrikumschichten (72, 82) über einer durch Maskentechnik hergestellten hoch dotierten Emitterzone (7) und einer hoch dotierten Kollektorzone (8) aufgebracht und strukturiert werden, so daß sich über einer herzustellenden Basiszone (9) in der Mitte zwischen Emitterzone (7) und Kollektorzone (8) ein Graben befindet, dann eine Hilfsschicht (11) ganzflächig konform mit konstanter Dicke (d) abgeschieden wird, wodurch der Graben der Breite (d) zu einem Spalt der Breite (x) der herzustellenden Basiszone (9) vermindert wird, durch diesen Spalt eine Implantation von Dotierstoff für das Vorzeichen der Leitfähigkeit der Basis vorgenommen wird, wobei die lateral zu dieser Basiszone (9) befindlichen Bereiche durch die die Flanken des Grabens bedeckenden vertikalen Anteile der Hilfsschicht (11) abgeschirmt werden, dann Kontaktlöcher in die Hilfsschicht (11) und die Dielektrikumschicht (72, 82) geätzt werden und Metallkontakte für den elektrischen Anschluß von Emitter, Kollektor und Basis hergestellt werden.
摘要翻译：一种用于SOI衬底上制造的横向双极型晶体管的过程中，发射极的导电类型和集电极的基本掺杂是在制备用于晶体管区的隔离区（5）外侧的设想来制备该SOI衬底，接触层（71，81的硅层）和介电层（72，82）被施加有由重掺杂发射极区域的掩模技术制造的膜（7）和一个高度掺杂的集电极区域（8）和构造成使得（在制造基区（9）在发射极区域之间的中部7）和集电极区域（8）是一沟槽，然后在具有恒定厚度（d）相一致的辅助层（11）在整个表面上沉积，从而使沟槽宽度（d），以一间隙宽度（x）由产生的基区被还原（9）中，通过该间隙进行的，掺杂剂的植入基底的导电的符号其中横向于该基区（9），其位于区域由沟槽的覆盖辅助层（11）的垂直部分的侧面被屏蔽，然后在辅助层（11）和所述电介质层的接触孔（72，82）被蚀刻和金属接触件用于的电连接由发射极，集电极和基极制成。

6. 发明公开

EP0552697A3 An SOI lateral bipolar transistor with a polysilicon emitter 失效
标题翻译：具有多晶硅发射极的SOI横向双极晶体管
公开(公告)号：EP0552697A3
公开(公告)日：1994-05-04
申请号：EP93100657.1
申请日：1993-01-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Davari, Bijan , Ning, Tak Hung , Shahidi, Ghavam Ghavami
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/66265 , H01L29/7317
摘要： The present invention solves the problems present in the prior art by forming a lateral emitter base junction of a bipolar transistor in which an N+ polysilicon layer forms the emitter. This is accomplished by attaching the polysilicon emitter to a vertical surface of the single crystal silicon. Single crystal silicon (102) is grown on a dielectric (104) and covered with another dielectric layer and an extrinsic base polysilicon layer (106). Polysilicon sidewall spacers (112) are formed as an edge strap connection between the extrinsic base and the single crystal silicon. The edge strap is isolated from the remainder of the device by a second sidewall spacer (114). An intrinsic base region (150) is formed in the single crystal silicon using the sidewall spacer as one defining edge of the intrinsic base region. The intrinsic base region (150) diffuses under the sidewall spacers. The single crystal silicon is etched to the underlying dielectric using the second sidewall spacer as one defining edge. This etch removes all the intrinsic base region except that under the sidewall spacers and leaves a vertical surface of the single crystal silicon exposed. This exposed vertical surface is the intrinsic base region. Conformal N type polysilicon (125) is then deposited to form an emitter contact on the vertical surface of the single crystal silicon intrinsic base region.
摘要翻译：本发明通过形成其中N +多晶硅层形成发射极的双极晶体管的横向发射极基极结解决了现有技术中存在的问题。这是通过将多晶硅发射极连接到单晶硅的垂直表面来完成的。在电介质（104）上生长单晶硅（102）并用另一介电层和外基极多晶硅层（106）覆盖。多晶硅侧壁间隔物（112）形成为非本征基底和单晶硅之间的边缘带连接。边缘带通过第二侧壁间隔件（114）与装置的其余部分隔离。使用侧壁间隔物作为本征基极区域的一个限定边缘，在单晶硅中形成本征基极区域（150）。内部基极区（150）在侧壁间隔层下扩散。使用第二侧壁间隔物作为一个限定边缘将单晶硅蚀刻到下面的电介质。这种蚀刻除去了侧壁间隔层之下的所有内部基区，并且使单晶硅的垂直表面露出。该暴露的垂直表面是本征基区。然后沉积共形N型多晶硅（125），以在单晶硅本征基区的垂直表面上形成发射极触点。

7. 发明公开

EP0060761A1 Transistor bipolaire latéral sur isolant et son procédé de fabrication 失效
标题翻译：侧向双极晶体管隔离器和Verfahren zu seiner Herstellung。
公开(公告)号：EP0060761A1
公开(公告)日：1982-09-22
申请号：EP82400388.3
申请日：1982-03-05
申请人： SOCIETE POUR L'ETUDE ET LA FABRICATION DE CIRCUITS INTEGRES SPECIAUX - E.F.C.I.S.
发明人： Mackowiak, Eugène , Borel, Joseph , Montier, Michel
IPC分类号： H01L29/72 , H01L29/10 , H01L29/60 , H01L29/62 , H01L21/285
CPC分类号： H01L29/66265 , H01L29/1008 , H01L29/42304 , H01L29/7317
摘要： L'invention concerne un transistor bipolaire NPN ou PNP réalisé selon une disposition latérale sur un substrat isolant (10).
Ce transistor comprend côte à côte une région d'émetteur (12), une région de base étroite (20) et une région de collecteur (14), toutes trois en silicium monocristallin, avec une couche de silicium polycristallin étroite (22) recouvrant exactement la région étroite de base et servant de conducteur d'accès à cette région. Un contact métallique est relié à cette région de silicium polycristallin, mais en dehors de la zone de base proprement dite entre l'émetteur et le collecteur, afin de ne pas risquer un court-circuit des jonctions par la métallisation. Ce transistor bipolaire est réalisable selon une technologie MOS.
摘要翻译： 1.一种绝缘层上的横向双极晶体管，包括： - 绝缘衬底（10）， - 由第一导电类型的掺杂硅制成的发射极区域（12）， - 由掺杂的硅制成的集电极区域（14）第一导电类型与第一导电类型分离，窄间隔， - 第二导电类型的掺杂硅的基极区域，在发射极和集电极区域之间的狭窄空间中延伸，发射极和集电极接触区域分别在发射极区域和集电极区域的硅上的金属沉积物（16,18）， - 与基底区域相邻的发射极和集电极区域的部分之上的氧化硅绝缘层（15），其特征在于 - 绝缘体层在基区之上呈现中断， - 掺杂有第二导电类型的杂质的低电阻率的多晶硅（22）的区域以窄带的形式延伸到基部区域上，该窄带可部分地在所述绝缘层上方并且与基底区域接触并且具有延伸超过发射器（12）和收集器区域（14）的终端区域（22），从而允许建立金属接触件（26），从而使该多晶硅硅片面积。

8. 发明授权

EP1771887B1 BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 失效转让
标题翻译：双极晶体管及其制造方法
公开(公告)号：EP1771887B1
公开(公告)日：2008-07-02
申请号：EP05759723.9
申请日：2005-07-07
申请人： NXP B.V.
发明人： MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/73 , H01L29/10 , H01L21/331
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 1019 and about 1020 at/cm3, and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).

9. 发明公开

EP1883955A2 METHOD OF FABRICATING A BIPOLAR TRANSISTOR 审中-公开
标题翻译：制造双极晶体管的方法
公开(公告)号：EP1883955A2
公开(公告)日：2008-02-06
申请号：EP06728018.0
申请日：2006-04-24
申请人： NXP B.V.
发明人： DONKERS, Johannes, J., T., M. , HIJZEN, Erwin , VAN NOORT, Wibo, D.
IPC分类号： H01L21/331 , H01L21/762 , H01L29/732 , H01L29/735 , H01L27/06
CPC分类号： H01L29/66272 , H01L21/76224 , H01L27/0641 , H01L27/0647 , H01L29/6625 , H01L29/66265 , H01L29/732 , H01L29/735
摘要： The invention provides a method for fabricating a bipolar transistor applying a standard shallow trench isolation fabrication method to simultaneously form a vertical bipolar transistor (29) or a lateral bipolar transistor (49) in a first trench (5, 50) and a shallow trench isolation region (27, 270) in a second trench (7, 70). Further, the fabrication method may simultaneously form a vertical bipolar transistor (27) in the first trench (5, 50), a lateral bipolar transistor (49) in a third trench and a shallow trench isolation region (27, 270) in the second trench (7, 70).
摘要翻译：本发明提供了一种用于制造应用标准浅沟槽隔离制造方法的双极晶体管的方法，以同时在第一沟槽（5,50）中形成垂直双极晶体管（29）或横向双极晶体管（49），并且浅沟槽隔离区域（27,270）在第二沟槽（7,70）中。此外，制造方法可以同时在第一沟槽（5,50）中形成垂直双极晶体管（27），在第三沟槽中形成横向双极晶体管（49），在第二沟槽中形成浅沟槽隔离区（27,270）沟槽（7,70）。

10. 发明公开

EP1696485A1 Process for manufacturing semiconductor devices in a SOI substrate with alignment marks 审中-公开
标题翻译：一种用于在SOI衬底制造的半导体器件具有对准标记的过程
公开(公告)号：EP1696485A1
公开(公告)日：2006-08-30
申请号：EP05425096.4
申请日：2005-02-24
申请人： STMicroelectronics S.r.l.
发明人： Leonardi, Salvatore , Modica, Roberto
IPC分类号： H01L23/544 , H01L21/762 , H01L21/8222 , H01L21/8232 , H01L21/8238 , H01L21/316
CPC分类号： H01L23/544 , H01L21/32 , H01L21/76286 , H01L21/8222 , H01L21/823481 , H01L21/823878 , H01L21/8249 , H01L29/66265 , H01L29/7317 , H01L29/7824 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Process for manufacturing an electronic semiconductor device, wherein a SOI wafer (20) is provided, formed by a bottom layer (21) of semiconductor material, an insulating layer (22), and a top layer (50) of semiconductor material, stacked on top of one another; alignment marks (32) are formed in the top layer; an implanted buried region (30) is formed, aligned to the alignment marks; a hard mask (52,53) is formed on top of the top layer (23;50) so as to align it to the alignment marks (32); using the hard mask, the top layer (23;50) is selectively removed so as to form a trench (55) extending up to the insulating layer (22); there a lateral-insulation region (60) in the trench (55), that is contiguous to the insulating layer (22) and delimits with the latter an insulated well (61) of semiconductor material; and electronic components (65-76) are formed in the top layer (23;50).
摘要翻译：用于制造电子半导体器件，worin一个SOI晶片（20）的过程被提供，由半导体材料的上绝缘层（22）的底层（21），和半导体材料的顶层（50），层叠形成彼此的顶部上; 对准标记（32）形成在所述顶层; 注入掩埋区（30）形成，对准的对准标记; 硬掩模（52,53）形成在所述顶层（23; 50）的顶部上，以便将其对准的对准标记（32）; 使用硬掩模，顶部层（23; 50）被选择性地去除以形成沟槽（55）一直延伸到绝缘层（22）; 在（55）有一横向绝缘区域（60）的沟槽所做的是邻接于绝缘层（22），并用绝缘良好的（61）的半导体材料的后界定; 和电子部件（65-76）形成在所述顶层（23; 50）。

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