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1. 发明申请

WO2006009850A3 SEMICONDUCTOR ASSEMBLY HAVING SUBSTRATE WITH ELECTROPLATED CONTACT PADS 审中-公开
标题翻译：具有电镀接触垫的基板的半导体组件
公开(公告)号：WO2006009850A3
公开(公告)日：2007-03-08
申请号：PCT/US2005021471
申请日：2005-06-17
申请人： TEXAS INSTRUMENTS INC , ABBOTT DONALD C
发明人： ABBOTT DONALD C
IPC分类号： H01L21/44 , H01L21/28 , H01L21/283 , H01L21/288 , H01L21/441 , H01L21/445 , H01L23/498 , H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07 , H01L31/108 , H05K1/11 , H05K3/24 , H05K3/34
CPC分类号： H05K3/244 , H01L23/498 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/039 , H01L2224/0401 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05573 , H01L2224/05644 , H01L2224/05664 , H01L2224/08501 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/81192 , H01L2224/81444 , H01L2224/81464 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H05K1/113 , H05K3/3463 , Y10S438/928 , H01L2924/00
摘要： An apparatus comprising an insulating substrate (101) having first and second surfaces (101a, 101b) and a plurality of metal-filled vias (102) extending from the first to the second surface. The first and second surfaces have contact pads (103, 104), each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer (110, copper) in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer (111 a, copper) secured to the seed metal layer, a second electroplated support layer (111 b, nickel), and at least one reflow metal bonding layer (112, palladium, gold) on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0 %), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors (220, 230) provide attachment to chip contact pads and external parts.
摘要翻译：一种包括具有第一和第二表面（101a，101b）和从第一表面延伸到第二表面的多个金属填充的通孔（102）的绝缘基板（101）的设备。第一和第二表面具有接触焊盘（103,104），每个接触焊盘包括至少一个通孔的连接器叠层。堆叠包括与通孔金属接触的种子金属层（110，铜），其能够提供用于在其表面上电镀的粘合剂和导电层，固定到种子金属层的第一电镀支撑层（111a，铜）第二电镀支撑层（111b，镍）和在第二支撑层上的至少一个回流金属结合层（112，钯，金）。电解电镀工艺产生基本上纯的（至少99.0％）的支撑层，没有不需要的添加剂如磷或硼，并且表现出紧密控制的晶粒尺寸。回流金属连接器（220,230）提供与芯片接触焊盘和外部部件的连接。

2. 发明申请

WO2003003369A1 マイクロ移動装置およびその製造方法审中-公开
标题翻译：微移动装置及其制造方法
公开(公告)号：WO2003003369A1
公开(公告)日：2003-01-09
申请号：PCT/JP2002/006433
申请日：2002-06-26
申请人：松下電器産業株式会社 , 中谷将也 , 森仲克也 , 三木勝政 , 多鹿博文
发明人：中谷将也 , 森仲克也 , 三木勝政 , 多鹿博文
IPC分类号： G11B21/10
CPC分类号： G11B5/5552 , Y10S438/928
摘要： A micro moving device for precisely positioning a disk−shaped recording medium used for, e.g., a recording/reproducing apparatus. A stabilized voltage is applied to an expandable body for changing the position of a recording head by application of a voltage. One end of the micro moving device is connected to a fixing substrate on which a recording head and so forth are mounted. The one end is secured to a fixing substrate so that the dimensions of the expandable body may not vary at the other end. An external electrode connection part for applying a voltage to the expandable body is provided in an area of the fixing substrate.
摘要翻译：一种用于精确定位用于例如记录/再现装置的盘形记录介质的微移动装置。将稳定的电压施加到可膨胀体，以通过施加电压来改变记录头的位置。微移动装置的一端连接到其上安装有记录头等的固定基板。一端固定在固定基板上，使得可扩张体的尺寸在另一端可能不变。在固定基板的一个区域中设置有用于向可膨胀体施加电压的外部电极连接部。

3. 发明申请

WO9636072A2 METHOD OF MANUFACTURING A DEVICE, BY WHICH METHOD A SUBSTRATE WITH SEMICONDUCTOR ELEMENT AND CONDUCTOR TRACKS IS GLUED TO A SUPPORT BODY WITH METALLIZATION 审中-公开
标题翻译：通过方法制造器件的方法将具有半导体元件和导体跟踪的基板用于具有金属化的支撑体
公开(公告)号：WO9636072A2
公开(公告)日：1996-11-14
申请号：PCT/IB9600350
申请日：1996-04-18
申请人： PHILIPS ELECTRONICS NV , PHILIPS NORDEN AB
发明人： MAAS HENRICUS GODEFRIDUS RAFAE , DEKKER RONALD , VAN DEURZEN MARIA HENRICA WILH
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/02 , H01L21/336 , H01L21/58 , H01L21/60 , H01L21/768 , H01L21/77 , H01L23/498 , H01L23/522 , H01L27/12 , H01L29/786 , H02M3/155 , H02M3/28 , H01L21/76
CPC分类号： H01L24/83 , H01L23/49811 , H01L24/29 , H01L24/81 , H01L2221/68368 , H01L2224/16 , H01L2224/24225 , H01L2224/2919 , H01L2224/81801 , H01L2224/8319 , H01L2224/8385 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , Y10S438/928 , Y10S438/977 , H01L2924/00
摘要： A method of manufacturing a device whereby a layer structure (15, 16; 15, 28) with semiconductor elements (5) and conductor tracks (14) is formed on a first side (2) of a semiconductor wafer (1) which is provided with a layer of semiconductor material (4) disposed on an insulating layer (3). Then the semiconductor wafer is fastened with said first side to a support wafer (18) by means of a glue layer (17), the support wafer being provided with a metallization (20). Material is then removed from the semiconductor wafer from the other, second side (19) thereof until the insulating layer is exposed. Contact windows (21) are provided in the insulating layer from the first side of the semiconductor wafer before the latter is fastened on the support wafer. These windows are filled with a material which can be removed selectively relative to the insulating layer. The contact windows are opened from the second side of the semiconductor wafer after the latter has been fastened on the support wafer and after the insulating layer has been exposed. Furthermore, openings (22) are formed in the layer structure and in the glue layer at the areas of the contact windows, which openings extend down to the metallization on the support wafer, after which the contact windows and the openings formed are provided with conductive elements. The expensive photolithographic equipment in the clean room can be used for this formation of the contact windows. Such equipment is then unnecessary in then space used for final mounting.
摘要翻译：一种制造器件的方法，其中在半导体晶片（1）的第一侧（2）上形成具有半导体元件（5）和导体轨道（14）的层结构（15,16; 15,28），所述第一侧（2）具有设置在绝缘层（3）上的半导体材料层（4）。然后，通过胶层（17）将半导体晶片与所述第一侧紧固到支撑晶片（18），所述支撑晶片设置有金属化（20）。然后从半导体晶片的另一个第二侧（19）去除材料直到绝缘层露出。接触窗（21）在半导体晶片的第一侧被固定在支撑晶片上之后设置在绝缘层中。这些窗口填充有可相对于绝缘层选择性地去除的材料。在半导体晶片被固定在支撑晶片上之后并且在绝缘层已经暴露之后，接触窗口从半导体晶片的第二侧被打开。此外，开口（22）形成在接触窗的区域中的层结构和胶层中，这些开口向下延伸到支撑晶片上的金属化，之后形成的接触窗和开口设置有导电元素。洁净室中昂贵的光刻设备可用于形成接触窗。这样的设备在当时用于最终安装的空间中是不必要的。

4. 发明申请

WO1994017553A1 THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：三维集成电路及其制造方法
公开(公告)号：WO1994017553A1
公开(公告)日：1994-08-04
申请号：PCT/US1994000363
申请日：1994-01-10
申请人： HUGHES AIRCRAFT COMPANY
发明人： HUGHES AIRCRAFT COMPANY , FINNILA, Ronald, M.
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L21/76895 , H01L21/76898 , H01L23/481 , H01L2224/16145 , H01L2225/06517 , H01L2225/06586 , H01L2225/06596 , H01L2924/01014 , H01L2924/13091 , Y10S438/928 , H01L2924/00
摘要： A method includes the steps of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI water includes a thin silicon layer (12) separated from a bulk silicon (10) substrate by a thin layer of dielectric material, typically SiO2 (11). A next step processes the thin silicon layers to form at least one electrical feedthrough (16) in each of the thin silicon layers (12) and to also form desired active and passive devices (17, 18, 19a, 19b) in each of the thin silicon layers. A next step forms interconnects (21) that overlie the thin silicon layer (12) and that are electrically coupled to the at least one feedthrough (16). One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then removed by a step of etching the bulk silicon substrate so as to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit of a desired complexity.
摘要翻译：一种方法包括提供第一和第二绝缘体上硅（SOI）晶片的步骤，其中每个SOI水包括通过介电材料薄层与本体硅（10）衬底分离的薄硅层（12），通常为SiO 2（11）。下一步骤处理薄硅层以在每个薄硅层（12）中形成至少一个电馈通（16），并且还在每个薄硅层（12）中形成期望的有源和无源器件（17,18,19a，19b）薄硅层。下一步骤形成覆盖在薄硅层（12）上并且与电源耦合到至少一个馈通（16）的互连（21）。然后将其中一个晶片附接到临时基板，使得互连被插入在薄硅层和临时基板之间。然后通过蚀刻体硅衬底的步骤去除具有临时衬底的晶片的体硅衬底，以暴露电介质层。然后通过暴露的电介质层形成进一步的互连，用于电接触至少一个馈通。这导致形成第一电路组件。接下来的步骤然后将电路组件的另外的互连件耦合到第二SOI晶片的互连，第二SOI晶片具有体基板，覆盖在衬底表面上的电介质层和覆盖在介电层上的处理硅层。然后移除临时底物。然后可以将附加电路组件堆叠并互连以形成具有期望复杂度的3d集成电路。

5. 发明申请

WO02054494A2 METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR MEMORY ARRANGEMENT 审中-公开
标题翻译：方法用于制造集成半导体存储器结构
公开(公告)号：WO02054494A2
公开(公告)日：2002-07-11
申请号：PCT/DE2001/004767
申请日：2001-12-14
IPC分类号： H01L21/8242 , H01L21/8246 , H01L27/06 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/00
CPC分类号： H01L27/108 , H01L27/0694 , H01L27/10808 , H01L27/1082 , H01L27/10835 , H01L27/10844 , H01L27/10852 , H01L27/10858 , H01L27/10861 , H01L27/11502 , H01L27/11507 , Y10S438/928
摘要： The invention relates to a method for producing an integrated semiconductor memory arrangement. According to said method, two capacitor modules (10, 20) are formed for each selection transistor (8) from the front and rear side of the substrate wafer (1) respectively. Said inventive process achieves a higher packing density of memory cells by the utilisation of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to "0" or "1" can also be saved for each selection transistor (8) in a ferroelectric memory arrangement, if the two capacitor modules have a different structure in terms of layer thickness, surface area or material.
摘要翻译：在制造集成半导体存储器结构，每个选择晶体管（8）的本发明方法具有形成在从前面和（1）前衬底晶片的背面每两个电容器模块（10，20）。通过利用该晶片背面上的更高的填充密度为所提出的处理流程可以通过存储单元来实现。具有相同小区区域可使用两次的读出信号。此外，在强电介质存储器件中，当两个电容器模块相对于厚度，面积或每地址材料，即构成不同每个选择晶体管（8）可为“0”或“1”被存储更多的状态。

6. 发明申请

WO01088970A1 SEMICONDUCTOR WAFER THINNING METHOD, AND THIN SEMICONDUCTOR WAFER 审中-公开
标题翻译： SEMICONDUCTOR WAFER THINNING METHOD，AND THIN SEMICONDUCTOR WAFER
公开(公告)号：WO01088970A1
公开(公告)日：2001-11-22
申请号：PCT/JP2001/003947
申请日：2001-05-11
IPC分类号： B24B7/22 , B24B37/30 , H01L21/304 , H01L21/687
CPC分类号： H01L21/304 , B24B7/228 , B24B41/068 , B24B49/00 , H01L21/6835 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , Y10S438/928 , Y10S438/959 , Y10S438/977
摘要： A method for thinning a semiconductor wafer having a semiconductor element (2) on its surface, by polishing the back thereof. This method comprises bonding the surface of the semiconductor wafer (1) to a support (4) through an adhesive layer; polishing the back of the semiconductor wafer while holding the support; and separating the thinned semiconductor wafer from the support. Preferably, a semiconductor wafer is employed as the support, and a thermally separable double-coated sheet is employed as the adhesive layer. The semiconductor wafer is heated and separated after ground. As a result, the semiconductor wafer having a thickness of 120 ñm or less can be manufactured at a low cost while suppressing the cracking or chipping to a minimum at the working step. Thus, there is provided a semiconductor wafer which is made thinner than those of the prior art while having a diameter as large as 150 mm or more.
摘要翻译：一种通过对其表面进行抛光来在其表面上稀薄具有半导体元件（2）的半导体晶片的方法。该方法包括通过粘合剂层将半导体晶片（1）的表面粘合到支撑体（4）上; 在保持支撑件的同时抛光半导体晶片的背面; 以及将薄化的半导体晶片与支撑体分离。优选地，使用半导体晶片作为支撑体，并且使用可热分离的双层片作为粘合剂层。研磨后将半导体晶片加热分离。结果，可以以低成本制造厚度为120μm以下的半导体晶片，同时在工作步骤中将破裂或碎裂抑制到最小。因此，提供了一种比现有技术薄的半导体晶片，同时具有大至150mm或更大的直径。

7. 发明申请

WO01078133A1 METHOD FOR EVALUATING IMPURITY CONCENTRATIONS IN SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：用于评估半导体衬底中的污染浓度的方法
公开(公告)号：WO01078133A1
公开(公告)日：2001-10-18
申请号：PCT/US2001/010775
申请日：2001-04-02
IPC分类号： H01L21/322 , H01L21/66
CPC分类号： H01L22/12 , H01L21/3221 , Y10S438/928 , Y10S438/974
摘要： A method for evaluating the concentration of impurities in a semiconductor substrate. The method includes drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces (12,14) of the substrate (10) to getter impurities from the substrate to the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were in the substrate prior to the drawing together.
摘要翻译：一种用于评估半导体衬底中的杂质浓度的方法。该方法包括将至少一部分杂质并排并在一起测量杂质的浓度。在本发明的一个实施例中，在衬底（10）的一个或多个表面（12,14）附近形成吸气层，以从衬底吸收杂质到吸气层。然后测量吸杂层的杂质浓度，并将结果用于确定在一起绘制之前在衬底中的至少一个杂质浓度范围。

8. 发明申请

WO01024240A1 METHOD FOR MANUFACTURING OF A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO01024240A1
公开(公告)日：2001-04-05
申请号：PCT/EP2000/009052
申请日：2000-09-15
IPC分类号： H01L21/302
CPC分类号： H01L21/302 , Y10S438/928
摘要： There is disclosed a method for manufacturing of a semiconductor wafer (1), preferably suitable for a wafer (1) with 300 mm in diameter or larger. After depositing at least one encapsulating material layer (14, 14') over the front side and back side of the wafer (1), the material layer (14) over the front side of the wafer (1) is etched selectively to form a predetermined structure in one of the following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer (14, 14'). By removing the material layer (14') over the back side of the wafer (1) partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. When applying e.g. a lithographic process over the front side of the wafer (1) in the further curse of the manufacturing process, non-linear overlay distortions caused by wafer warpage are minimized.
摘要翻译：公开了一种用于制造半导体晶片（1）的方法，优选地适用于直径为300mm或更大的晶片（1）。在晶片（1）的前侧和后侧上沉积至少一个密封材料层（14,14'）之后，选择性地蚀刻在晶片（1）的前侧上的材料层（14）以形成在以下工艺步骤之一中的预定结构。晶片翘曲是由于材料层（14,14'）的不平坦的晶片弯曲应力引起的。通过根据所期望的弓形应力晶片的减小部分地或完全地去除晶片（1）背面上的材料层（14'），翘曲减小。当应用例如在制造过程的进一步诅咒中，在晶片（1）的前侧上的光刻工艺，由晶片翘曲引起的非线性覆盖失真最小化。

9. 发明申请

WO00044045A1 MICROCIRCUIT DIE-SAWING PROTECTOR AND METHOD 审中-公开
公开(公告)号：WO00044045A1
公开(公告)日：2000-07-27
申请号：PCT/US2000/001269
申请日：2000-01-18
IPC分类号： H01L21/00 , H01L21/78 , B26F3/00 , H01L21/304
CPC分类号： H01L21/67132 , H01L21/67092 , H01L21/6836 , H01L21/78 , H01L2221/68327 , H01L2224/32225 , Y10S438/928
摘要： A method and apparatus for protecting hypersensitive microcircuits (2) on the face of a semiconductor wafer (1) from contamination and mechanical damage during die sawing and subsequent die handling operations include the provision of a plastic sheet (26) having an array of protective domes (28) formed into it. Each die (3) in the semiconductor wafer (1) is covered by a respective one of the domes (28), with an associated one of the microcircuits (2) protectively sealed therein. Die sawing is performed with the component side of the semiconductor wafer (1) facing up. The invention enables the use of conventional die-handling equipment and results in improved device yield.
摘要翻译：用于保护半导体晶片（1）的表面上的过敏微电路（2）的方法和装置不受模具切割和随后的模具处理操作期间的污染和机械损坏，包括提供具有保护圆顶阵列的塑料片（26）（28）形成。半导体晶片（1）中的每个管芯（3）被相应的一个圆顶（28）覆盖，其中一个微电路（2）被保护地密封在其中。在半导体晶片（1）的组件侧面朝上进行模切。本发明能够使用常规的模具处理设备并导致提高的装置产量。

10. 发明申请

WO1996005617A1 IMPROVED WAFER AND METHOD OF MAKING SAME 审中-公开
标题翻译：改进的波形及其制作方法
公开(公告)号：WO1996005617A1
公开(公告)日：1996-02-22
申请号：PCT/US1995007521
申请日：1995-06-12
申请人： THE CHARLES STARK DRAPER LABORATORY, INC.
发明人： THE CHARLES STARK DRAPER LABORATORY, INC. , BERNSTEIN, Jonathan, J.
IPC分类号： H01L29/06
CPC分类号： G01H11/06 , H01L27/20 , Y10S148/028 , Y10S438/928
摘要： A wafer and a method of making a wafer containing a plurality of severable transducer chips includes a wafer; a plurality of transducer chips formed on the wafer; and a grid of longitudinal and latitudinal grooves in the wafer for separating the chips from each other and enabling them to be easily, individually severed from the wafer, as well as a transducer chip and a method of making it, having integrally raised contacts adapted for a flip chip or beam lead interconnection, with a transducer formed on the chip; and a plurality of raised contacts integrally formed with the chip and electrically interconnected with the transducer.
摘要翻译：晶片和制造包含多个可分离换能器芯片的晶片的方法包括晶片; 形成在晶片上的多个换能器芯片; 以及晶片中的纵向和纬向格栅，用于将芯片彼此分离并使其能够容易地从晶片切断，以及换能器芯片及其制造方法，具有适于倒装芯片或光束引线互连，其上形成有在芯片上的换能器; 以及与所述芯片一体形成并与所述换能器电互连的多个凸起接触件。

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