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1. 发明申请

WO1994017557A1 THERMALLY MATCHED READOUT/DETECTOR ASSEMBLY AND METHOD FOR FABRICATING SAME 审中-公开
标题翻译：热匹配读出/检测器组件及其制造方法
公开(公告)号：WO1994017557A1
公开(公告)日：1994-08-04
申请号：PCT/US1994000370
申请日：1994-01-10
申请人： HUGHES AIRCRAFT COMPANY
发明人： HUGHES AIRCRAFT COMPANY , FINNILA, Ronald, M. , MALLOY, Gerard, T. , BENDIK, Joseph, J.
IPC分类号： H01L27/146
CPC分类号： B23K20/023 , B23K20/16 , B23K35/004 , H01L21/6835 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/167 , H01L25/50 , H01L27/1465 , H01L2221/68363 , H01L2221/68368 , H01L2221/68381 , H01L2224/0401 , H01L2224/05624 , H01L2224/13109 , H01L2224/16145 , H01L2224/291 , H01L2224/29188 , H01L2224/2919 , H01L2224/32225 , H01L2224/73253 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/83005 , H01L2224/83805 , H01L2224/83825 , H01L2224/8385 , H01L2224/8389 , H01L2224/92 , H01L2224/92143 , H01L2224/92242 , H01L2924/01004 , H01L2924/01049 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10329 , H01L2924/13091 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2224/11 , H01L2924/00
摘要： An integrated circuit assembly includes a silicon thin film circuit bonded to a substrate of a material selected to provide the assembly with an effective thermal expansion characteristic that approximately matches that of another device, such as HgCdTe detector. The assembly, when bump bonded with the device, is resistant to failure when subjected to thermal cycling. A first method for manufacturing the assembly includes the steps of forming a desired circuit in a thin layer (12) of silicon on a silicon substrate of a bonded silicon wafer. The thin silicon layer including the circuit is then bonded to the selected substrate material (24). Thereafter the silicon substrate is removed and the resulting assembly may be mated to the device (36). A second method employs a two stage transfer technique wherein the processed thin silicon layer is bonded to a first, temporary substrate; the silicon substrate is removed; a second, permanent substrate is attached; and the first substrate is removed. The second substrate is comprised of a material selected for providing the assembly with a coefficient of thermal expansion that is matched to the material of the device.
摘要翻译：集成电路组件包括被粘合到材料的衬底上的硅薄膜电路，所述材料被选择以提供与其它器件（例如HgCdTe检测器）的热膨胀特性近似匹配的有效热膨胀特性。当与装置碰撞时，组件在受到热循环时具有抗故障的能力。用于制造组件的第一种方法包括以下步骤：在粘合的硅晶片的硅衬底上的硅薄层（12）中形成所需的电路。包括电路的薄硅层然后被结合到所选择的衬底材料（24）上。此后，去除硅衬底，并将得到的组件与配件（36）配合。第二种方法采用二阶段转移技术，其中处理的薄硅层结合到第一临时衬底; 去除硅衬底; 附上第二个永久基片; 并且去除第一衬底。第二基板由选择用于为组件提供与该装置的材料匹配的热膨胀系数的材料组成。

2. 发明申请

WO1994017553A1 THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：三维集成电路及其制造方法
公开(公告)号：WO1994017553A1
公开(公告)日：1994-08-04
申请号：PCT/US1994000363
申请日：1994-01-10
申请人： HUGHES AIRCRAFT COMPANY
发明人： HUGHES AIRCRAFT COMPANY , FINNILA, Ronald, M.
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L21/76895 , H01L21/76898 , H01L23/481 , H01L2224/16145 , H01L2225/06517 , H01L2225/06586 , H01L2225/06596 , H01L2924/01014 , H01L2924/13091 , Y10S438/928 , H01L2924/00
摘要： A method includes the steps of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI water includes a thin silicon layer (12) separated from a bulk silicon (10) substrate by a thin layer of dielectric material, typically SiO2 (11). A next step processes the thin silicon layers to form at least one electrical feedthrough (16) in each of the thin silicon layers (12) and to also form desired active and passive devices (17, 18, 19a, 19b) in each of the thin silicon layers. A next step forms interconnects (21) that overlie the thin silicon layer (12) and that are electrically coupled to the at least one feedthrough (16). One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then removed by a step of etching the bulk silicon substrate so as to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit of a desired complexity.
摘要翻译：一种方法包括提供第一和第二绝缘体上硅（SOI）晶片的步骤，其中每个SOI水包括通过介电材料薄层与本体硅（10）衬底分离的薄硅层（12），通常为SiO 2（11）。下一步骤处理薄硅层以在每个薄硅层（12）中形成至少一个电馈通（16），并且还在每个薄硅层（12）中形成期望的有源和无源器件（17,18,19a，19b）薄硅层。下一步骤形成覆盖在薄硅层（12）上并且与电源耦合到至少一个馈通（16）的互连（21）。然后将其中一个晶片附接到临时基板，使得互连被插入在薄硅层和临时基板之间。然后通过蚀刻体硅衬底的步骤去除具有临时衬底的晶片的体硅衬底，以暴露电介质层。然后通过暴露的电介质层形成进一步的互连，用于电接触至少一个馈通。这导致形成第一电路组件。接下来的步骤然后将电路组件的另外的互连件耦合到第二SOI晶片的互连，第二SOI晶片具有体基板，覆盖在衬底表面上的电介质层和覆盖在介电层上的处理硅层。然后移除临时底物。然后可以将附加电路组件堆叠并互连以形成具有期望复杂度的3d集成电路。

3. 发明申请

WO1994017549A1 OFF-CHIP CONDUCTOR STRUCTURE AND FABRICATION METHOD FOR LARGE INTEGRATED MICROCIRCUITS 审中-公开
标题翻译：用于大型集成微处理器的片外导体结构和制造方法
公开(公告)号：WO1994017549A1
公开(公告)日：1994-08-04
申请号：PCT/US1994000373
申请日：1994-01-10
申请人： HUGHES AIRCRAFT COMPANY
发明人： HUGHES AIRCRAFT COMPANY , WILLIAMS, Ronald, L. , FINNILA, Ronald, M.
IPC分类号： H01L21/48
CPC分类号： H01L23/50 , H01L21/4857 , H01L21/68 , H01L23/147 , H01L23/5385 , H01L24/48 , H01L25/0652 , H01L2224/48227 , H01L2224/48228 , H01L2924/00014 , H01L2924/01014 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2224/45099
摘要： A silicon carrier wafer (82) is thermally processed to produce a silicon dioxide layer (12) on a surface thereof. A patterned metal conductor layer (16) is formed on the silicon dioxide layer (12) using silicon processing technology which enables high resolution and density. A silicon nitride layer (14) is formed on the conductor layer (16) and exposed areas of the silicon dioxide layer (12). Vias (32, 34, 36) are formed through the silicon nitride layer (14) for ohmic contact to appropriate points of the conductor layer (16). Thick metal contact layers (38, 40, 42, 44, 46, 48) are formed on the silicon nitride layer (14) in ohmic connection with the vias (32, 34, 36), and indium bumps (50, 52, 54) are formed on the contact layers (38, 40, 42, 44, 46, 48). The carrier (82), which serves as a support during processing, is removed by etching, with the silicon dioxide layer (12) acting as an etch stop. Integrated circuit chips (18) are mounted on the silicon dioxide layer (2) and connected to the conductor pattern through openings (24, 26) formed in the silicon dioxide layer (12). A substrate (56) which has electrical circuitry (58, 60, 62, 76) and bumps (70, 72, 74) formed thereon is adhered to the silicon nitride layer (14), with the circuitry (58, 60, 62, 76) being connected to the conductor layer (16) by the bumps (50, 52, 54, 70, 72, 74). The conductor layer (16) provides power and other interconnects for the chips (18) and circuitry (58, 60, 62, 76) on the substrate (56), thereby increasing the size and density of circuit integration and improving heat dissipation.
摘要翻译：硅载体晶片（82）被热处理以在其表面上产生二氧化硅层（12）。使用能够实现高分辨率和密度的硅处理技术，在二氧化硅层（12）上形成图案化的金属导体层（16）。在导体层（16）和二氧化硅层（12）的暴露区域上形成氮化硅层（14）。通孔（32,34,36）通过氮化硅层（14）形成，以与导体层（16）的适当点欧姆接触。厚度的金属接触层（38,40,44,44,46,48）形成在氮化硅层（14）上，与通孔（32,34,36）欧姆连接，铟凸块（50,52,54））形成在接触层（38,40,42,44,46,48）上。在处理期间用作支撑体的载体（82）通过蚀刻被去除，二氧化硅层（12）用作蚀刻停止。集成电路芯片（18）安装在二氧化硅层（2）上，并通过形成在二氧化硅层（12）中的开口（24,26）连接到导体图案。具有形成在其上的电路（58,60,62,76）和凸块（70,72,74）的衬底（56）被粘附到氮化硅层（14）上，电路（58,60,62,76） 76）通过所述凸块（50,52,54,70,72,74）连接到所述导体层（16）。导体层（16）为衬底（56）上的芯片（18）和电路（58,60,62,76）提供功率和其它互连，从而增加电路集成的尺寸和密度并改善散热。

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