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1. 发明申请

WO2004023519A2 HIGH-DENSITY NROM-FINFET 审中-公开
标题翻译： HIGH POET NROM的FinFET
公开(公告)号：WO2004023519A2
公开(公告)日：2004-03-18
申请号：PCT/EP0309297
申请日：2003-08-21
申请人： INFINEON TECHNOLOGIES AG , HOFMANN FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SPECHT MICHAEL
发明人： HOFMANN FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SPECHT MICHAEL
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792 , H01R11/22 , H01R13/62 , H01L
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： The invention relates to a semiconductor memory comprising a plurality of memory cells, each memory cell comprising the following: a first conductively doped contact area (S/D), a second conductively doped contact area (S/D) and a channel region arranged therebetween, which are embodied in a plate-type rib (FIN) made of a semiconductor material and which are arranged successively in the above-mentioned order in the longitudinal direction of the rib (FIN), said rib (FIN) having a substantially rectangular shape, according to a cross-sectional view extending in a perpendicular manner with respect to the longitudinal direction of the rib (FIN), comprising an upper rib side (10) and opposite lateral rib surfaces (12, 14); a memory layer (18) which is embodied in order to program the memory cell and which is arranged on the upper rib side (10) and distanced by means a first insulating layer (20), said memory layer (18) protruding over at least one (12) of the lateral rib surfaces (12) in a normal direction of one lateral rib surface (12), such that said one lateral rib surface (12) and the upper rib surface (10) form an injection edge (16) for injecting charge carriers from the channel region into the memory layer (18); and at least one gate electrode (WL1) which is distanced by means of a second insulating layer (22) from said one lateral rib surface (12) and distanced by means of a third insulating layer (29) from the memory layer (18), said gate electrode (WL1) being electrically insulated in relation to the channel region and being embodied in order to control the electrical conductivity thereof.
摘要翻译：本发明涉及一种具有多个存储器单元，每个存储器单元包括一个半导体存储器：第一导电掺杂接触区（S / D），第二导电掺杂接触区（S / D）和一个介于沟道区，其中（在网状肋FIN ）形成的半导体材料，以及（在肋FIN的纵向方向上按此次序）被布置成一个在另一个后面，其中所述鳍（FIN）至少在垂直（在沟道区延伸到所述肋FIN的长度方向）截面，具有一肋顶部的大致rechtsecksförmige形状（10）和相对的肋的侧表面（12，14）; 所设计的用于通过第一绝缘体层编程所述存储器单元存储层（18）（20）间隔开的肋顶部（10）布置，其中，在一个正常的方向经由肋的侧表面中的至少一个（12）（12）的存储层（18）肋侧表面（12）突出，以使所述一个肋侧表面（12）和肋顶部（10）形成用于从沟道区的载流子到所述存储层注入（18）的喷射边缘（16）; 和至少一个栅极电极（WL1），其通过第二绝缘体层隔开一个（22）的肋侧表面（12）和通过所述存储层（18）的第三绝缘层（29），其中所述沟道区相对的栅电极（WL1），其电是绝缘的，并适于控制其导电性。

2. 发明申请

WO2003069675A1 半導体装置及びその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2003069675A1
公开(公告)日：2003-08-21
申请号：PCT/JP2003/001602
申请日：2003-02-14
申请人：松下電器産業株式会社 , 小川久 , 宮永績 , 江利口浩二 , 山田隆順 , 糸長総一郎 , 森義弘
发明人：小川久 , 宮永績 , 江利口浩二 , 山田隆順 , 糸長総一郎 , 森義弘
IPC分类号： H01L27/108
CPC分类号： H01L27/10882 , H01L27/10829 , H01L27/10894 , Y10S257/905 , Y10S257/908
摘要： A memory region is provided with a memory cell transistor and a trench type capacitor, and a logic circuit region with CMOS transistors. A bit line contact (31) and a bit line (31) extending over an interlayer insulating film (30) are provided. In the memory cell transistor, a source diffused layer (18) is covered with two insulating film side walls (25a, 25b), but no silicide layer is formed over the top of the source diffused layer. A plate contact (31) is provided to connect a shield line (33) and a plate electrode (16b) by penetrating the interlayer insulating film (30), and this shield line (33) is provided on the same wiring layer as the bit line (32).
摘要翻译：存储区域设置有存储单元晶体管和沟槽型电容器，以及具有CMOS晶体管的逻辑电路区域。提供了位于层间绝缘膜（30）上的位线接触（31）和位线（31）。在存储单元晶体管中，源极扩散层（18）被两个绝缘膜侧壁（25a，25b）覆盖，但在源极扩散层顶部没有形成硅化物层。提供了通过穿透层间绝缘膜（30）来连接屏蔽线（33）和平板电极（16b）的板状触点（31），并且该屏蔽线（33）设置在与该位行（32）。

3. 发明申请

WO02056383A1 SEMICONDUCTOR STORAGE DEVICE AND ITS MANUFACTURING METHOD 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：WO02056383A1
公开(公告)日：2002-07-18
申请号：PCT/JP2001/011672
申请日：2001-12-28
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10894 , H01L27/10885 , H01L28/55 , H01L28/60 , Y10S257/905 , Y10S257/908
摘要： A memory cell of a DRAM that is a semiconductor storage device has a bit line (21a) connected to a bit line plug (20b) and a local wiring (21b) on a first interlayer insulation film (18). The side face of a hard mask (37), an upper barrier metal (36), a Pt film, and a BST film (34) is overlaid with a conductor side wall (40) made of TiAlN. No contact is provided on the Pt film (35) which constitutes an upper electrode (35a), but the upper electrode (35a) is connected to an upper layer wiring (Cu wiring 42) by a conductor side wall (40), dummy lower electrode (33b), a dummy cell plug (30), and a local wiring (21b). Since the Pt film (35) is not exposed to a reductive atmosphere, a capacitor insulation film (34a) is prevented from deteriorating in characteristics.
摘要翻译：作为半导体存储装置的DRAM的存储单元具有连接到第一层间绝缘膜（18）上的位线插头（20b）和局部布线（21b）的位线（21a）。硬掩模（37），上阻挡金属（36），Pt膜和BST膜（34）的侧面与由TiAlN制成的导体侧壁（40）重叠。在构成上电极（35a）的Pt膜（35）上没有提供接触，但是上电极（35a）通过导体侧壁（40）连接到上层布线（Cu布线42），虚拟下部电极（33b），虚拟电池插头（30）和局部布线（21b）。由于Pt膜（35）没有暴露于还原气氛中，所以防止电容器绝缘膜（34a）的特性劣化。

4. 发明申请

WO1994003898A1 DRAM CELL ASSEMBLY 审中-公开
标题翻译： DRAM单元安排
公开(公告)号：WO1994003898A1
公开(公告)日：1994-02-17
申请号：PCT/DE1993000542
申请日：1993-06-23
申请人： SIEMENS AKTIENGESELLSCHAFT , RÖSNER, Wolfgang
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G11C11/00
CPC分类号： H01L27/10808 , Y10S257/905 , Y10S257/908
摘要： The invention concerns a DRAM cell assembly in which two memory cells, which include a MOS transistor and a memory element, are each designed as a pair of transistors (10) whose source regions are connected to each other and to a bit line (11). The drain, gate electrode and source of the MOS transistors are disposed in a straight line which is aligned in the same direction as the bit lines (11) and which is disposed essentially below one bit line (11). Adjacent to each drain region is a connection zone (13) which is located beside associated bit lines (11) and by means of which a cell contact is established to the memory element. The cell assembly is particularly suitable for buried-bitline stacked-capacitor (BBSTC) DRAM cells.

5. 发明申请

WO1985003167A1 SEMICONDUCTOR STRUCTURE WITH RESISTIVE FIELD SHIELD 审中-公开
标题翻译：具有电阻场的半导体结构
公开(公告)号：WO1985003167A1
公开(公告)日：1985-07-18
申请号：PCT/US1984002079
申请日：1984-12-18
申请人： AMERICAN TELEPHONE & TELEGRAPH COMPANY
发明人： AMERICAN TELEPHONE & TELEGRAPH COMPANY , COMIZZOLI, Robert, Benedict
IPC分类号： H01L29/06
CPC分类号： H01L29/405 , H01L29/402 , H01L29/408 , Y10S257/905
摘要： A segmented semi-insulating polysilicon (SIPOS) layer (26) is used between electrodes (20, 22) making contact to the surface of a silicon device in order to shield the surface from the effects of charge on dielectric layers above the surface so as to maintain breakdown voltages. The segmenting of the SIPOS layer significantly increases the resistance thereof and therey limits leakage generated by the layer without significantly reducing its shielding capability.

6. 发明申请

WO2003107425A2 SEMICONDUCTOR DEVICE HAVING FERROELECTRIC FILM AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有电磁膜的半导体器件及其制造方法
公开(公告)号：WO2003107425A2
公开(公告)日：2003-12-24
申请号：PCT/JP2003/007431
申请日：2003-06-11
申请人： KABUSHIKI KAISHA TOSHIBA , INFINEON TECHNOLOGIES AG
发明人： KANAYA, Hiroyuki , HILLIGER, Andreas
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , H01L27/10855 , H01L27/11507 , Y10S257/905
摘要： A B S T R A C T First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first and second semiconductor regions. An interlayer insulating film is formed on the semiconductor substrate to cover the first and second semiconductor regions and the gate electrode. First and second lower electrodes are formed on the interlayer insulating film. A first contact plug is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug is formed in the interlayer insulating film in contact with the second lower electrode. A first ferroelectric film is formed on the first lower electrode. A first upper electrode is formed on the first ferroelectric film. A second ferroelectric film is formed on the second lower electrode. A second upper electrode is formed on the second ferroelectric film.
摘要翻译： A B S T R A C T第一和第二半导体区域在半导体衬底中彼此分开形成。在位于第一和第二半导体区域之间的半导体衬底的上方形成栅电极。在半导体衬底上形成层间绝缘膜以覆盖第一和第二半导体区域和栅电极。第一和第二下电极形成在层间绝缘膜上。在与第一下电极接触的层间绝缘膜中形成第一接触插塞。在与第二下电极接触的层间绝缘膜中形成第二接触插塞。第一铁电体膜形成在第一下部电极上。第一上电极形成在第一铁电体膜上。在第二下部电极上形成第二铁电体膜。第二上电极形成在第二铁电体膜上。

7. 发明申请

WO2002103703A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2002103703A2
公开(公告)日：2002-12-27
申请号：PCT/EP2002/006495
申请日：2002-06-05
申请人： INNOVATIVE SILICON SA , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FAZAN, Pierre, Christophe , OKHONIN, Serguei
发明人： FAZAN, Pierre, Christophe , OKHONIN, Serguei
IPC分类号： G11C11/404
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中数据存储单元形成在衬底13上。每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。主体22中的净电荷的大小可以通过施加到晶体管的输入信号进行调整，并且可以通过在栅极28和栅极28之间施加电压信号来至少部分地抵消由输入信号调节净电荷漏极22和源极18与漏极22之间。

8. 发明申请

WO01099152A2 BURIED BIT LINE-FIELD PLATE ISOLATION DEFINED ACTIVE SEMICONDUCTOR AREAS 审中-公开
标题翻译： BINIED BIT LINE-FIELD PLATE ISOLATION DEFINED ACTIVE SEMICONDUCART AREAS
公开(公告)号：WO01099152A2
公开(公告)日：2001-12-27
申请号：PCT/US2001/019813
申请日：2001-06-21
IPC分类号： H01L27/108 , H01L
CPC分类号： H01L27/10805 , Y10S257/905 , Y10S257/907
摘要： Active areas (24A,24B) of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines (BL1, BL2, BL3) on two sides and by conductors (20) separated from the semiconductor substrate by electrically insulating layers (22) on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion therof, commonly known as field plate insulation. Each buried bit line is formed in a trench (14) in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator (16) and has a conductor (18A) in a bottom portion thereof. Common drain regions (23A) shared by two transistors are coupled to conductors (18A) by means of a conductor (32).
摘要翻译：形成在半导体衬底上的动态随机存取存储器（DRAM）的有效区域（24A，24B）由两侧的掩埋位线（BL1，BL2，BL3）以及与半导体衬底分开的导体（20）绝缘层（22）在另外两侧。在DRAM的操作期间，导体被电偏置，以使半导体衬底的部分在其中大部分载流子浓度增加，从而抑制反转，通常称为场板绝缘。每个掩埋位线形成在半导体衬底中的沟槽（14）中。每个沟槽容纳单独的位线并且衬有电绝缘体（16），并且在其底部具有导体（18A）。由两个晶体管共享的公共漏极区域（23A）通过导体（32）耦合到导体（18A）。

9. 发明申请

WO2006025901A2 DEVICE FOR SUBTRACTING OR ADDING CHARGE IN A CHARGE-COUPLED DEVICE 审中-公开
标题翻译：用于在充电耦合器件中放电或增加充电的装置
公开(公告)号：WO2006025901A2
公开(公告)日：2006-03-09
申请号：PCT/US2005019362
申请日：2005-06-03
申请人： MASSACHUSETTS INST TECHNOLOGY , ANTHONY MICHAEL P
发明人： ANTHONY MICHAEL P
IPC分类号： H01L31/113 , H01L27/148 , H01L31/00 , H04N5/347 , H04N5/372
CPC分类号： H04N5/347 , H04N5/372 , Y10S257/905
摘要： The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a "wire transfer" device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.
摘要翻译：本发明提供了一种用于在数据包穿过CCD时向CCD中的电荷分组加或减量量的装置。该装置使用“有线传输”装置结构来在充电数据包遍历装置期间执行电荷的加或减。一对电互连的扩散结合在电荷耦合路径内，以提供当分组穿过CCD时能从分组中加或减的电荷量。

10. 发明申请

WO2004105090A2 STRUCTURE AND METHOD FOR FORMING A TRENCH MOSFET HAVING SELF-ALIGNED FEATURES 审中-公开
标题翻译：用于形成具有自对准特征的TRENCH MOSFET的结构和方法
公开(公告)号：WO2004105090A2
公开(公告)日：2004-12-02
申请号：PCT/US2004015059
申请日：2004-05-14
申请人： FAIRCHILD SEMICONDUCTOR , HERRICK ROBERT , LOSEE BECKY , PROBST DEAN
发明人： HERRICK ROBERT , LOSEE BECKY , PROBST DEAN
IPC分类号： H01L21/336 , H01L29/417 , H01L29/78 , H01L
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/7802 , Y10S257/905
摘要： In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.
摘要翻译：根据本发明的实施例，半导体器件如下形成。定义可以除去硅的硅层的暴露的表面积。去除硅层的一部分以形成从硅层的暴露的表面区域延伸到硅层中的沟槽的中间部分。定义可以除去硅的硅层的额外暴露表面积。去除硅层的附加部分以形成沟槽的外部部分，使得沟槽的外部部分从硅层的附加暴露表面区域延伸到硅层中。沟槽的中间部分比沟槽的外部部分更深地延伸到硅层中。

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