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1. 发明申请

WO2004027778A1 CHAIN MEMORY ARCHITECTURE 审中-公开
标题翻译：链接存储器架构
公开(公告)号：WO2004027778A1
公开(公告)日：2004-04-01
申请号：PCT/EP2003/010477
申请日：2003-09-19
申请人： INFINEON TECHNOLOGIES AG , KABUSHIKI KAISHA TOSHIBA
发明人： HILLIGER, Andreas , JACOB, Michael , OZAKI, Toru , ROEHR, Thomas , SHUTO, Susumo
IPC分类号： G11C11/22
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.
摘要翻译：公开了一种用于串行存储器架构的改进的单元设计。改进的电池设计有助于使用单一蚀刻工艺形成电容器，而不是如常规要求的那样。在一个实施例中，电容器对的每个电容器设置有与两个相邻单元晶体管的公共扩散区域接触的至少一个插头。在另一个实施例中，使用与一对电容器的底部电极具有足够重叠的大插头。

2. 发明申请

WO2004093168A1 A PROCESS FOR FABRICATION OF FERROELECTRIC DEVICES WITH REDUCED HYDROGEN ION DAMAGE 审中-公开
标题翻译：具有降低氢损伤的电磁装置的制造方法
公开(公告)号：WO2004093168A1
公开(公告)日：2004-10-28
申请号：PCT/SG2004/000065
申请日：2004-03-22
申请人： INFINEON TECHNOLOGIES AG , KABUSHIKI KAISHA TOSHIBA , HORNIK, Karl , ZHUANG, Haoren , MOON, Bum-Ki , HILLIGER, Andreas , NATORI, Katsuaki
发明人： HORNIK, Karl , ZHUANG, Haoren , MOON, Bum-Ki , HILLIGER, Andreas , NATORI, Katsuaki
IPC分类号： H01L21/02
CPC分类号： H01L28/57 , H01L21/02178 , H01L21/022 , H01L21/02266 , H01L21/0228 , H01L21/28568 , H01L21/3141 , H01L21/31616 , H01L28/65 , H01L28/75
摘要： A ferrocapacitor device comprising a ferroelectric capacitor structure which includes a bottom electrode (5), a ferroelectric layer (7), and a top electrode (9), formed over a substructure (1). A first Al 2 0 3 cover layer (15) is deposited over the structure by a physical vapour deposition process (such as sputtering), and a second Al 2 0 3 cover layer (17) is deposited over the first Al 2 0 3 cover layer (15) by atomic layer deposition. The first Al 2 0 3 cover layer (15) protects the capacitor structure during the formation of the second Al 2 0 3 cover layer (17), and the second Al 2 0 3 cover layer (17) protects the capacitor structure during back end processes performed on the FeRAM device.
摘要翻译：一种铁电体器件，包括形成在子结构（1）上的包括底部电极（5），铁电体层（7）和顶部电极（9）的铁电电容器结构。通过物理气相沉积工艺（例如溅射）在结构上沉积第一Al 2 O 3覆盖层（15），并且通过原子层沉积在第一Al 2 O 3覆盖层（15）上沉积第二Al 2 O 3覆盖层（17）。第一Al 2 O 3覆盖层（15）在形成第二Al 2 O 3覆盖层（17）期间保护电容器结构，并且第二Al 2 O 3覆盖层（17）在对FeRAM器件执行的后端处理期间保护电容器结构。

3. 发明申请

WO2004068539A2 SIDEWALL STRUCTURE AND METHOD OF FABRICATION FOR REDUCING OXYGEN DIFFUSION TO CONTACT PLUGS DURING CW HOLE REACTIVE ION ETCH PROCESSING 审中-公开
标题翻译：用于在CW孔反应离子处理期间减少氧化物扩散到接触片的制造结构和方法
公开(公告)号：WO2004068539A2
公开(公告)日：2004-08-12
申请号：PCT/SG2004/000018
申请日：2004-01-19
申请人： INFINEON TECHNOLOGIES AG , KABUSHIKI KAISHA TOSHIBA , ZHUANG, Haoren , EGGER, Ulrich , TOMIOKA, Kazuhiro , LIAN, Jingyu , NAGEL, Nicolas , HILLIGER, Andreas , BEITEL, Gerhard
发明人： ZHUANG, Haoren , EGGER, Ulrich , TOMIOKA, Kazuhiro , LIAN, Jingyu , NAGEL, Nicolas , HILLIGER, Andreas , BEITEL, Gerhard
IPC分类号： H01L
CPC分类号： H01L28/55 , H01L21/31116 , H01L28/57
摘要： The present invention provides a sidewall oxygen diffusion barrier and method for fabricating the sidewall oxygen diffusion barrier to reduce the diffusion of oxygen to contact plugs during CW hole reactive ion etch processing of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence, while in another embodiment the sidewall barrier is formed by etching back an oxygen barrier.
摘要翻译：本发明提供一种侧壁氧扩散阻挡层和用于制造侧壁氧扩散阻挡层的方法，以在FeRAM器件的铁电电容器的CW孔反应离子蚀刻处理期间减少氧气对接触插塞的扩散。在一个实施例中，侧壁屏障由衬底栅栏形成，而在另一个实施例中，侧壁屏障是通过蚀刻回氧屏障形成的。

4. 发明申请

WO2003107425A3 SEMICONDUCTOR MEMORY DEVICE HAVING A FERROELECTRIC CAPACITOR AND A MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：WO2003107425A3
公开(公告)日：2003-12-24
申请号：PCT/JP2003/007431
申请日：2003-06-11
申请人： KABUSHIKI KAISHA TOSHIBA , INFINEON TECHNOLOGIES AG
发明人： KANAYA, Hiroyuki , HILLIGER, Andreas
IPC分类号： H01L27/115
摘要： In a TC parallel unit series connected ferroelectric memory, an interlayer insulating film (15, 16) is formed on a semiconductor substrate (11) to cover first and second semiconductor regions (12) and a gate electrode (14). First and second lower electrodes (18A, 18B) of ferroelectric capacitors are formed on the interlayer insulating film (16). A first contact plug (21A) is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug (21B) is formed in the interlayer insulating film in contact with the second lower electrode. First and second contact plugs are connected to a buried interconnection (22) which is connected to one of said semiconductor regions by a third contact plug (23). In another embodiment, first to third contact plugs and the buried interconnection are replaced by a single contact plug (36).

5. 发明申请

WO2003060955A2 BARRIER STACK WITH IMPROVED BARRIER PROPERTIES 审中-公开
标题翻译：具有改进障碍物质的障碍物堆叠
公开(公告)号：WO2003060955A2
公开(公告)日：2003-07-24
申请号：PCT/EP2003/000114
申请日：2003-01-08
申请人： INFINEON TECHNOLOGIES AG , KABUSHIKI KAISHA TOSHIBA
发明人： NAGEL, Nicolas , IMAI, Keitaro , BEITEL, Gerhard, Adolf , HILLIGER, Andreas , MOON, Bum-Ki , YAMAKAWA, Koji
IPC分类号： H01L
CPC分类号： H01L27/11502 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers having mismatched grain boundaries. The barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second barrier layer.
摘要翻译：公开了用于抑制诸如O 2的原子或分子扩散的改进的阻挡层。势垒堆叠在电容器超过插塞结构中特别有用，以防止插塞氧化，这可能不利地影响结构的可靠性。阻挡层包括具有不匹配晶界的第一和第二阻挡层。阻挡层选自例如Ir，Ru，Pd，Rh或其合金。通过提供错配的晶界，这些层的界面阻挡了氧的扩散路径。为了进一步增强阻挡性能，使用例如快速热氧化，用O 2钝化第一阻挡层。 RTO在第一阻挡层的表面上形成薄的氧化物层。氧化物层可有利地促进第一和第二阻挡层的晶界的失配。

6. 发明申请

WO2004077532A1 METHODS OF FORMING ELECTRICAL CONNECTIONS WITHIN FERROELECTRIC DEVICES 审中-公开
标题翻译：在电磁设备中形成电气连接的方法
公开(公告)号：WO2004077532A1
公开(公告)日：2004-09-10
申请号：PCT/SG2004/000040
申请日：2004-02-20
申请人： INFINEON TECHNOLOGIES AG , KABUSHIKI KAISHA TOSHIBA , GERNHARDT, Stefan , HIDAKA, Osamu , LIAN, Jenny , BRUCHHAUS, Rainer , HILLIGER, Andreas , NAGEL, Nicolas
发明人： GERNHARDT, Stefan , HIDAKA, Osamu , LIAN, Jenny , BRUCHHAUS, Rainer , HILLIGER, Andreas , NAGEL, Nicolas
IPC分类号： H01L21/02
CPC分类号： H01L21/7687 , H01L21/76802 , H01L23/26 , H01L28/55 , H01L28/75 , H01L2924/0002 , Y10T29/4902 , Y10T29/49155 , Y10T29/49156 , H01L2924/00
摘要： A fabrication process for ferroelectric capacitors includes forming openings (23, 30), in the device, into which electrically conductive material (28, 37) can be inserted to form electrical connections within the device. The surface of each opening is coated with a layer (24, 34) of getter material which absorbs contaminants (25, 31, 33) formed during the opening process. This means that in subsequent processing steps the contaminants do not vagabond towards the ferroelectric layers (7) of the device where they might otherwise cause damage, for example during a subsequent crystallisation stage.
摘要翻译：用于铁电电容器的制造工艺包括在器件中形成开口（23,30），导电材料（28,37）可插入该开口以形成器件内的电连接。每个开口的表面涂覆有吸收材料层（24,34），其吸收在打开过程中形成的污染物（25,31,33）。这意味着在随后的处理步骤中，污染物不会流向设备的铁电层（7），否则可能会导致损坏，例如在随后的结晶阶段。

7. 发明申请

WO2004027871A1 CAPACITOR OVER PLUG STRUCTURE 审中-公开
标题翻译：电容器通过插头结构
公开(公告)号：WO2004027871A1
公开(公告)日：2004-04-01
申请号：PCT/EP2003/008947
申请日：2003-08-12
申请人： INFINEON TECHNOLOGIES AG , KABUSHIKI KAISHA TOSHIBA
发明人： BEITEL, Gerhard , HILLIGER, Andreas , MOON, Bum-Ki , NAGEL, Nicolas , TSUCHIYA, Takamichi , YABUKI, Moto
IPC分类号： H01L27/115
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/60 , H01L28/90
摘要： A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.
摘要翻译：公开了一种电容器插头（COP）结构。 COP避免了常规COP结构中产生的步骤，这对电容器的性能产生不利影响。在一个实施例中，通过提供具有上部和下部的插塞来避免该步骤。耦合到电容器的底部电极的上部具有与底部电极基本相同的表面积。可以在塞子和底部电极之间提供阻挡层以避免塞子材料的氧化。

8. 发明申请

WO2003107425A2 SEMICONDUCTOR DEVICE HAVING FERROELECTRIC FILM AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有电磁膜的半导体器件及其制造方法
公开(公告)号：WO2003107425A2
公开(公告)日：2003-12-24
申请号：PCT/JP2003/007431
申请日：2003-06-11
申请人： KABUSHIKI KAISHA TOSHIBA , INFINEON TECHNOLOGIES AG
发明人： KANAYA, Hiroyuki , HILLIGER, Andreas
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , H01L27/10855 , H01L27/11507 , Y10S257/905
摘要： A B S T R A C T First and second semiconductor regions are formed separately from each other in a semiconductor substrate. A gate electrode is formed above the semiconductor substrate which lies between the first and second semiconductor regions. An interlayer insulating film is formed on the semiconductor substrate to cover the first and second semiconductor regions and the gate electrode. First and second lower electrodes are formed on the interlayer insulating film. A first contact plug is formed in the interlayer insulating film in contact with the first lower electrode. A second contact plug is formed in the interlayer insulating film in contact with the second lower electrode. A first ferroelectric film is formed on the first lower electrode. A first upper electrode is formed on the first ferroelectric film. A second ferroelectric film is formed on the second lower electrode. A second upper electrode is formed on the second ferroelectric film.
摘要翻译： A B S T R A C T第一和第二半导体区域在半导体衬底中彼此分开形成。在位于第一和第二半导体区域之间的半导体衬底的上方形成栅电极。在半导体衬底上形成层间绝缘膜以覆盖第一和第二半导体区域和栅电极。第一和第二下电极形成在层间绝缘膜上。在与第一下电极接触的层间绝缘膜中形成第一接触插塞。在与第二下电极接触的层间绝缘膜中形成第二接触插塞。第一铁电体膜形成在第一下部电极上。第一上电极形成在第一铁电体膜上。在第二下部电极上形成第二铁电体膜。第二上电极形成在第二铁电体膜上。

9. 发明申请

WO2003060955A3 BARRIER STACK WITH IMPROVED BARRIER PROPERTIES 审中-公开
公开(公告)号：WO2003060955A3
公开(公告)日：2003-07-24
申请号：PCT/EP2003/000114
申请日：2003-01-08
申请人： INFINEON TECHNOLOGIES AG , KABUSHIKI KAISHA TOSHIBA
发明人： NAGEL, Nicolas , IMAI, Keitaro , BEITEL, Gerhard, Adolf , HILLIGER, Andreas , MOON, Bum-Ki , YAMAKAWA, Koji
IPC分类号： H01L21/02
摘要： An improved barrier stack (390) for inhibiting diffusion of atoms or molecules, such as O 2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers (347, 348) having mismatched grain boundaries. The barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O 2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second barrier layer.

10. 发明申请

WO2004090949A1 SUPPRESSION OF ELECTRODE RE-CRYSTALLISATION IN A FERROCAPACITOR 审中-公开
标题翻译：抑制FERROCAPACITOR中的电极重结晶
公开(公告)号：WO2004090949A1
公开(公告)日：2004-10-21
申请号：PCT/SG2004/000086
申请日：2004-04-08
申请人： INFINEON TECHNOLOGIES AG , GERNHARDT, Stefan , LIAN, Jingyu , BRUCHHAUS, Rainer , HILLIGER, Andreas , NAGEL, Nicolas , WELLHAUSEN, Uwe
发明人： GERNHARDT, Stefan , LIAN, Jingyu , BRUCHHAUS, Rainer , HILLIGER, Andreas , NAGEL, Nicolas , WELLHAUSEN, Uwe
IPC分类号： H01L21/02
CPC分类号： H01L28/55 , H01L28/60
摘要： An electrode (1) of a ferrocapacitor formed by an etching process is treated by oxygen implantation to reduce the size of crystal domains (15) in side regions (11) of the electrode (1). Subsequently a cover layer (3) is deposited over the side wall of the electrode to protect the ferrocapacitor in subsequent process steps. Later in the fabrication process the ferrocapacitor is subject to heat treatments, but due to the reduced size of the crystal domains (15) the growth of the crystal domains in the side regions (11) of the electrode is more homogenous, and causes reduced stresses in the cover layer (3), leading to a reduced risk of the cover layer (3) failing to protect the ferrocapacitor.
摘要翻译：通过氧注入处理通过蚀刻工艺形成的二茂铁电极的电极（1），以减小电极（1）的侧面区域（11）中的晶体畴（15）的尺寸。随后，在电极的侧壁上沉积覆盖层（3），以在随后的工艺步骤中保护铁电体电容器。在制造过程中，铁电体经受热处理，但是由于晶体畴的尺寸减小（15），电极的侧面区域（11）中的晶体畴的生长更均匀，导致应力降低在覆盖层（3）中，导致覆盖层（3）不能保护铁电体的风险降低。

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