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1. 发明申请

WO2009031052A3 ZERO-CAPACITOR (FLOATING BODY) RANDOM ACCESS MEMORY CIRCUITS WITH POLYCIDE WORD LINES AND MANUFACTURING METHODS THEREFOR 审中-公开
标题翻译：零电容（浮动体）带多边形字线的随机存取电路及其制造方法
公开(公告)号：WO2009031052A3
公开(公告)日：2009-08-06
申请号：PCT/IB2008003284
申请日：2008-03-21
申请人： INNOVATIVE SILICON SA , FAZAN PIERRE
发明人： FAZAN PIERRE
IPC分类号： H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/78
CPC分类号： H01L27/10805 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/10847 , H01L27/1203 , H01L29/7841
摘要： Embodiments of a manufacturing process flow for producing memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.
摘要翻译：用于生产可以实现4F2或5F2的数量级的位单元大小的存储器件的制造工艺流程的实施例，并且可以应用于公共源极/漏极，单独的源极/漏极或仅公共源极或仅公共的仅漏极晶体管阵列。有源区域和字线图案在绝缘体上硅衬底上形成为垂直布置的直线。活动区域和字线间的交点定义用于连接通孔和金属线层的接触区域。使用绝缘间隔物来提供蚀刻掩模图案，其允许将接触区域选择性地蚀刻为一系列线性沟槽，从而便于直线光刻技术。制造过程的实施例在连续的处理步骤中去除第一层金属（金属-1）岛并形成细长的通孔以构建密集的存储器阵列。

2. 发明申请

WO2007098044A3 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A3
公开(公告)日：2008-10-16
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)
摘要翻译：用于读取，写入和/或操作具有一个或多个电浮动体晶体管的多位存储单元（以及具有多个这样的存储单元的存储单元阵列）的多位存储单元和电路和技术，其中电荷是存储在电浮体晶体管的体区中。多位存储器单元存储多于一个的数据位（例如，二，三，四，五，六等）和/或两个以上的数据状态（例如，三，四，五，六等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件的一部分（例如，分立存储器）

3. 发明申请

WO2007128738A1 SEMICONDUCTOR MEMORY CELL AND ARRAY USING PUNCH-THROUGH TO PROGRAM AND READ SAME 审中-公开
标题翻译：半导体存储单元和阵列使用PUNCH-THROUGH编程和读取它们
公开(公告)号：WO2007128738A1
公开(公告)日：2007-11-15
申请号：PCT/EP2007/054227
申请日：2007-04-30
申请人： INNOVATIVE SILICON SA , OKHONIN, Serguei , NAGOGA, Mikhail
发明人： OKHONIN, Serguei , NAGOGA, Mikhail
IPC分类号： G11C11/404 , H01L27/108 , H01L29/78
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch- through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.
摘要翻译：一种集成电路器件（例如逻辑或分立存储器件），包括一个包括穿通型晶体管的存储器单元，其中该晶体管包括一个源极区，一个漏极区，一个栅极，一个栅极绝缘体以及一个具有存储节点至少部分地位于栅极绝缘体的正下方。存储单元包括代表身体区域中的存储节点中的电荷量的至少两个数据状态。第一电路耦合到存储单元的穿通模式晶体管，以：（1）产生第一和第二组写入控制信号，以及（2a）将第一组写入控制信号施加到晶体管以写入第一数据状态，并且（2b）将第二组写入控制信号施加到晶体管以在存储器单元中写入第二数据状态。响应于第一组写入控制信号，穿通模式晶体管经由冲击电离至少提供身体区域中的第一电荷。晶体管可以设置在体型衬底或SOI型衬底上。

4. 发明申请

WO2007126830A2 MEMORY ARRAY HAVING A PROGRAMMABLE WORD LENGTH, AND METHOD OF OPERATING SAME 审中-公开
标题翻译：具有可编程字长度的记忆阵列及其操作方法
公开(公告)号：WO2007126830A2
公开(公告)日：2007-11-08
申请号：PCT/US2007007591
申请日：2007-03-29
申请人： INNOVATIVE SILICON SA , CARMAN ERIC
发明人： CARMAN ERIC
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/1048 , G11C11/404 , G11C11/4087 , G11C11/4093 , G11C2211/4016 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10879 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed.
摘要翻译：具有存储单元阵列的存储单元阵列和器件（即集成电路器件，例如逻辑器件（例如，微控制器或微处理器）或存储器件（例如，分立存储器））包括电浮置其中电荷存储在晶体管的主体中的体晶体管，以及用于读取，控制和/或操作这样的存储单元阵列和这种器件的技术。存储单元阵列和器件包括可变和/或可编程的字长。字长涉及所选择的一行存储器单元的选定存储单元（其通过地址数据确定）。在一个实施例中，字长可以是所选行的任何数量的存储器单元，其小于或等于存储器阵列的所选行的存储器单元的总数。在一个方面，可以针对存储器阵列的选定行的所选择的存储器单元执行写入和/或读取操作，同时所选行的未选择的存储器单元不受干扰。

5. 发明申请

WO03088322A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO03088322A2
公开(公告)日：2003-10-23
申请号：PCT/EP0302748
申请日：2003-03-17
申请人： INNOVATIVE SILICON SA , FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
发明人： FAZAN PIERRE CHRISTOPHE , OKHONIN SERGUEI
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/739 , H01L29/786 , H01L29/788 , H01L21/00
CPC分类号： H01L29/78696 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10873 , H01L27/1203 , H01L29/7391 , H01L29/7841 , H01L29/78648 , H01L29/7881
摘要： A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).
摘要翻译：公开了诸如DPAM存储器件的半导体器件。 A，半导体材料的基板（12）设置有箱形区域（38）形式的能带修改装置，并被绝缘层（14）覆盖。半导体层（16）具有形成在其中的源极（18）和漏极（20）区域，以限定各个场效应晶体管的主体（22）。盒区域（38）比相邻体（22）更重掺杂，但是比相应的源极（18）和漏极（20）掺杂得较少，并且改变了本体（22）的价态和/或导带，以增加可以存储在身体（22）中的电荷量。

6. 发明申请

WO2002103703A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2002103703A2
公开(公告)日：2002-12-27
申请号：PCT/EP2002/006495
申请日：2002-06-05
申请人： INNOVATIVE SILICON SA , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FAZAN, Pierre, Christophe , OKHONIN, Serguei
发明人： FAZAN, Pierre, Christophe , OKHONIN, Serguei
IPC分类号： G11C11/404
CPC分类号： H01L27/108 , G11C11/403 , G11C11/404 , G11C11/5621 , G11C2211/4016 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841 , H04N5/3355 , Y10S257/905 , Y10S257/907 , Y10S438/982
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.
摘要翻译：公开了诸如存储器件或辐射检测器的半导体器件，其中数据存储单元形成在衬底13上。每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。主体22中的净电荷的大小可以通过施加到晶体管的输入信号进行调整，并且可以通过在栅极28和栅极28之间施加电压信号来至少部分地抵消由输入信号调节净电荷漏极22和源极18与漏极22之间。

7. 发明申请

WO2008090475A3 FLOATING-BODY DRAM TRANSISTOR COMPRISING SOURCE/DRAIN REGIONS SEPARATED FROM THE GATED BODY REGION 审中-公开
标题翻译：包含源自区域的源/排放区域的浮动体DRAM晶体管
公开(公告)号：WO2008090475A3
公开(公告)日：2009-04-30
申请号：PCT/IB2008000980
申请日：2008-01-24
申请人： INNOVATIVE SILICON SA , OKHONIN SERGUEI
发明人： OKHONIN SERGUEI
IPC分类号： H01L27/108 , G11C11/404 , H01L29/78
CPC分类号： H01L27/1203 , G11C7/00 , G11C11/40 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region (18) and a gate (16) is disposed over a first portion (18-1) of the body region. The device includes a source region (20) adjoining a second portion (18-2) of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region (22) adjoining a third portion (18-3) of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该装置包括电浮动体区域（18），并且在身体区域的第一部分（18-1）之上设置有栅极（16）。该装置包括与本体区域的第二部分（18-2）邻接的源极区域（20），邻近第一部分的第二部分并且将源区域与第一部分分离。所述装置包括邻接所述主体区域的第三部分（18-3）的漏极区域（22），所述第三部分与所述第一部分相邻并且将所述漏极区域与所述第一部分分开。

8. 发明申请

WO2008002513A2 INTEGRATED CIRCUIT HAVING MEMORY ARRAY INCLUDING ECC AND/OR COLUMN REDUNDANCY, AND METHOD OF PROGRAMMING, CONTROLLING AND/OR OPERATING SAME 审中-公开
标题翻译：具有存储器阵列的集成电路，包括ECC和/或冗余冗余，以及编程，控制和/或操作的方法
公开(公告)号：WO2008002513A2
公开(公告)日：2008-01-03
申请号：PCT/US2007014679
申请日：2007-06-25
申请人： INNOVATIVE SILICON SA , SINGH ANANT PRATAP
发明人： SINGH ANANT PRATAP
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G01J3/02 , G01J3/0291 , G01J3/10 , G01J3/28 , G01J2003/1213 , G01J2003/2866 , G01N2201/129 , G06F11/1048 , G11C7/1006 , G11C29/846 , G11C2029/0409 , G11C2207/104
摘要： An integrated circuit device (for example, a logic device or a memory device (such as, a discrete memory device)), including a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, multiplexer circuitry, coupled to the memory cell array, wherein the multiplexer circuitry includes a plurality of data multiplexers, each data multiplexer having a plurality of inputs, including (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs, and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.
摘要翻译：集成电路器件（例如，逻辑器件或存储器件（例如，分立存储器件）），包括具有排列成行和列的矩阵的多个存储单元的存储单元阵列，多路复用器电路其中所述多路复用器电路包括多个数据多路复用器，每个数据多路复用器具有多个输入，所述多个输入包括：（i）用于接收写数据的第一输入，所述第一输入代表要写入所述存储器单元的存储单元的数据所述存储单元阵列响应于写入操作，以及（ii）第二输入端，用于接收表示从所述存储单元阵列的存储单元读取的数据的读取数据，以及相关联的输出以响应于从所述多个存储单元阵列中的一个输出数据耦合到多路复用器电路的输入和校正子产生电路，以产生：（i）使用该读数据的写数据校正子向量和（ii）使用该读数据的读数据校正子向量。

9. 发明申请

WO2007098044A8 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A8
公开(公告)日：2007-11-29
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).
摘要翻译：这里描述的许多发明以及这些发明的许多方面和实施例，例如多位存储器单元以及用于读取，写入和/或操作多位存储器单元（以及具有多个这样的存储单元）具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。多比特存储单元存储多于一个的数据位（例如，两个，三个，四个，五个，六个等等）和/或两个以上的数据状态（例如，三个，四个，五个，六个等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件（例如，分立存储器）的一部分。

10. 发明申请

WO2003088322A3 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2003088322A3
公开(公告)日：2003-10-23
申请号：PCT/EP2003/002748
申请日：2003-03-17
申请人： INNOVATIVE SILICON SA , FAZAN, Pierre, Christophe , OKHONIN, Serguei
发明人： FAZAN, Pierre, Christophe , OKHONIN, Serguei
IPC分类号： H01L29/786
摘要： A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).

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