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1. 发明申请

WO2006066890A1 BIPOLAR READING TECHNIQUE FOR A MEMORY CELL HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR 审中-公开
标题翻译：具有电浮动体晶体管的记忆体的双极读取技术
公开(公告)号：WO2006066890A1
公开(公告)日：2006-06-29
申请号：PCT/EP2005/013755
申请日：2005-12-21
申请人： INNOVATIVE SILICON S.A. , OKHONIN, Serguei , NAGOGA, Mikhail
发明人： OKHONIN, Serguei , NAGOGA, Mikhail
IPC分类号： H01L29/78 , H01L27/108 , G11C11/404
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016 , H01L27/1023 , H01L27/108 , H01L29/78 , H01L29/7841
摘要： A technique of sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, the present inventions are directed to a memory cell, having an electrically floating body transistor, and/or a technique of reading the data state in such a memory cell. In this regard, the present inventions employ the intrinsic bipolar transistor current to read and/or determine the data state of the electrically floating body memory cell (for example, whether the electrically floating body memory cell is programmed in a State "0" and State "'I"). During the read operation, the data state is determined primarily by or sensed substantially using the bipolar current responsive to the read control signals and significantly less by the interface channel current component, which is negligible relatively to the bipolar component. The bipolar transistor current may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor. As such, the programming window obtainable with the bipolar reading technique may be considerably higher (for example, up two orders of magnitude higher) than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component.
摘要翻译：一种对存储单元阵列（例如具有由电浮体晶体管组成的多个存储单元的存储单元阵列）的存储单元的数据状态进行采样，检测，读取和/或确定的技术。在一个实施例中，本发明涉及具有电浮体晶体管的存储单元，和/或在这种存储单元中读取数据状态的技术。在这方面，本发明使用本征双极晶体管电流来读取和/或确定电浮动体存储单元的数据状态（例如，电浮动体存储单元是否被编程在状态“0”和状态 “'一世”）。在读取操作期间，数据状态主要由或基本上使用响应于读取的控制信号的双极性电流确定，并且显着地小于相对于双极组件可忽略的界面通道电流分量。由于本征双极晶体管的高增益，双极晶体管电流可能对浮体电位非常敏感。因此，采用双极读取技术可获得的编程窗口可以比采用常规读取技术（主要基于接口通道电流分量的编程窗口）高得多（例如，高两个数量级）。

2. 发明申请

WO2007098044A3 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A3
公开(公告)日：2008-10-16
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)
摘要翻译：用于读取，写入和/或操作具有一个或多个电浮动体晶体管的多位存储单元（以及具有多个这样的存储单元的存储单元阵列）的多位存储单元和电路和技术，其中电荷是存储在电浮体晶体管的体区中。多位存储器单元存储多于一个的数据位（例如，二，三，四，五，六等）和/或两个以上的数据状态（例如，三，四，五，六等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件的一部分（例如，分立存储器）

3. 发明申请

WO2007028583A1 MEMORY CELL AND MEMORY CELL ARRAY HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHODS OF OPERATING SAME 审中-公开
标题翻译：具有电浮动体晶体管的存储单元和存储单元阵列及其操作方法
公开(公告)号：WO2007028583A1
公开(公告)日：2007-03-15
申请号：PCT/EP2006/008668
申请日：2006-09-06
申请人： INNOVATIVE SILICON S.A. , OKHONIN, Serguei , NAGOGA, Mikhail
发明人： OKHONIN, Serguei , NAGOGA, Mikhail
IPC分类号： G11C11/404 , G11C11/4076
CPC分类号： G11C11/409 , G11C11/404 , G11C11/4067 , G11C11/4076 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
摘要翻译：写入，编程，保持，维护，采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态（例如，具有多个存储器单元的存储器单元阵列的技术）电浮体晶体管）。一方面，本发明涉及用于控制和/或操作半导体存储单元（以及具有多个这样的存储单元的存储单元阵列以及包括存储单元阵列的集成电路器件）的技术，其具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。本发明的技术可以采用双极晶体管电流来控制，写入和/或读取这种存储单元中的数据状态。在这方面，本发明可以采用双极晶体管电流来控制，写入和/或读取存储单元的电浮体晶体管中的数据状态。

4. 发明申请

WO2008090475A3 FLOATING-BODY DRAM TRANSISTOR COMPRISING SOURCE/DRAIN REGIONS SEPARATED FROM THE GATED BODY REGION 审中-公开
标题翻译：包含源自区域的源/排放区域的浮动体DRAM晶体管
公开(公告)号：WO2008090475A3
公开(公告)日：2009-04-30
申请号：PCT/IB2008000980
申请日：2008-01-24
申请人： INNOVATIVE SILICON SA , OKHONIN SERGUEI
发明人： OKHONIN SERGUEI
IPC分类号： H01L27/108 , G11C11/404 , H01L29/78
CPC分类号： H01L27/1203 , G11C7/00 , G11C11/40 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region (18) and a gate (16) is disposed over a first portion (18-1) of the body region. The device includes a source region (20) adjoining a second portion (18-2) of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region (22) adjoining a third portion (18-3) of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该装置包括电浮动体区域（18），并且在身体区域的第一部分（18-1）之上设置有栅极（16）。该装置包括与本体区域的第二部分（18-2）邻接的源极区域（20），邻近第一部分的第二部分并且将源区域与第一部分分离。所述装置包括邻接所述主体区域的第三部分（18-3）的漏极区域（22），所述第三部分与所述第一部分相邻并且将所述漏极区域与所述第一部分分开。

5. 发明申请

WO2007098044A8 MULTI-BIT MEMORY CELL HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND METHOD OF PROGRAMMING AND READING SAME 审中-公开
标题翻译：具有电浮标体晶体管的多位存储单元及其编程和读取方法
公开(公告)号：WO2007098044A8
公开(公告)日：2007-11-29
申请号：PCT/US2007004163
申请日：2007-02-15
申请人： INNOVATIVE SILICON SA , CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
发明人： CARMAN ERIC , OKHONIN SERGUEI , JONES MARK-ERIC
IPC分类号： G11C11/34
CPC分类号： H01L29/7841 , G11C7/1006 , G11C7/16 , G11C11/404 , G11C11/565 , G11C2211/4016
摘要： There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).
摘要翻译：这里描述的许多发明以及这些发明的许多方面和实施例，例如多位存储器单元以及用于读取，写入和/或操作多位存储器单元（以及具有多个这样的存储单元）具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。多比特存储单元存储多于一个的数据位（例如，两个，三个，四个，五个，六个等等）和/或两个以上的数据状态（例如，三个，四个，五个，六个等等）值得注意的是，存储单元阵列可以包括集成电路器件的一部分，例如逻辑器件（例如，微处理器）或存储器件（例如，分立存储器）的一部分。

6. 发明申请

WO2004102576A3 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING SAME 审中-公开
公开(公告)号：WO2004102576A3
公开(公告)日：2004-11-25
申请号：PCT/US2004/014691
申请日：2004-05-11
申请人： INNOVATIVE SILICON, INC. , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
发明人： FERRANT, Richard , OKHONIN, Serguei , CARMAN, Eric , BRON, Michel
IPC分类号： G11C11/00
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

7. 发明申请

WO2003088322A3 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2003088322A3
公开(公告)日：2003-10-23
申请号：PCT/EP2003/002748
申请日：2003-03-17
申请人： INNOVATIVE SILICON SA , FAZAN, Pierre, Christophe , OKHONIN, Serguei
发明人： FAZAN, Pierre, Christophe , OKHONIN, Serguei
IPC分类号： H01L29/786
摘要： A semiconductor device such as a DPAM memory device is disclosed. A, Substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).

8. 发明申请

WO2002103703A3 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2002103703A3
公开(公告)日：2002-12-27
申请号：PCT/EP2002/006495
申请日：2002-06-05
申请人： INNOVATIVE SILICON SA , ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL) , FAZAN, Pierre, Christophe , OKHONIN, Serguei
发明人： FAZAN, Pierre, Christophe , OKHONIN, Serguei
IPC分类号： G11C11/404
摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

9. 发明申请

WO2009039169A1 REFRESHING DATA OF MEMORY CELLS WITH ELECTRICALLY FLOATING BODY TRANSISTORS 审中-公开
标题翻译：用电浮动体晶体管刷新记忆细胞数据
公开(公告)号：WO2009039169A1
公开(公告)日：2009-03-26
申请号：PCT/US2008/076666
申请日：2008-09-17
申请人： INNOVATIVE SILICON S.A. , CARMAN, Eric , NAGOGA, Mikhail , OKHONIN, Serguei
发明人： CARMAN, Eric , NAGOGA, Mikhail , OKHONIN, Serguei
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： A semiconductor device along with circuits including the same and methodsof operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括一个包括一个晶体管的存储单元。晶体管包括栅极，电浮体区域，以及与体区相邻的源极区域和漏极区域。存储在设备的存储单元中的数据可以在单个时钟周期内刷新

10. 发明申请

WO2008090475A2 SEMICONDUCTOR DEVICE WITH ELECTRICALLY FLOATING BODY 审中-公开
标题翻译：具有电动浮体的半导体器件
公开(公告)号：WO2008090475A2
公开(公告)日：2008-07-31
申请号：PCT/IB2008/000980
申请日：2008-01-24
申请人： INNOVATIVE SILICON S.A. , OKHONIN, SERGUEI
发明人： OKHONIN, SERGUEI
CPC分类号： H01L27/1203 , G11C7/00 , G11C11/40 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described, The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.
摘要翻译：描述了半导体器件以及包括其的电路及其操作方法。该器件包括电浮体区域，并且栅极设置在身体区域的第一部分之上。该装置包括与该区域的第二部分邻接的源极区域，该第二部分与该第一部分相邻并且将该源区域与该第一部分分开。该装置包括与该区域的第三部分邻接的漏极区域，该第三部分与该第一部分相邻并且将该漏极区域与该第一部分分开。

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